ASICS Design Verification Engineer

Qualcomm

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $115,600–$173,400 / yr
Posted: 3 days ago
Closes: Dec 20, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $191k

This role $144k

$102k most similar roles pay here $241k

This role pays less than 88% of similar roles. Most pay $165,400–$216,250 — the shaded band above. At the midpoint, this role pays about $144k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 807 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 487 roles with salary data.

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At a glance

TL;DR · ASICS Design Verification Engineer

Role Posting Log in to save

Join Qualcomm Technologies as a Senior Digital Power IP Verification Engineer on their cutting-edge team responsible for the entire verification lifecycle of digital power IPs from concept to post-silicon support. This role involves comprehensive pre-silicon test planning, developing advanced SystemVerilog-UVM testbenches, coverage and assertion models, formal verification properties, and deploying UPF verification flows. You will also develop automation scripts in Perl or Python to enhance verification efficiency. Ideal candidates have a Master’s degree in Computer Science, Electrical Engineering, or related fields with extensive experience in ASIC design and verification methodologies like UVM/OVM, digital RTL languages such as SystemVerilog, and formal verification techniques. Experience with AMBA bus protocols is beneficial but not required.

Skills

SystemVerilog UVM SystemVerilog-UVM Perl Python C++ C VHDL Formal Verification Assertion Based Formal Verification AMBA Bus Protocol AXI AHB APB

What you'll do

Develop comprehensive pre-silicon test plans for digital power IP.
Create and maintain advanced verification methodologies using SystemVerilog-UVM.
Design coverage models and assertion-based formal verification properties.
Implement power-aware UPF verification flows and methodologies.
Automate verification processes to enhance efficiency and accuracy.

What we're looking for

2+ years of ASIC design and verification tools experience
Bachelor's degree in Engineering, Science, or related field
Experience with SystemVerilog-UVM for testbench development
Skills in coverage, assertion model, and formal verification development
Proficiency in scripting/automation using Perl or Python
Knowledge of digital design concepts and RTL languages like Verilog/SystemVerilog

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