ASICS Design Verification Engineer
Qualcomm
At a glance
AI generatedJoin Qualcomm Technologies as a Senior Digital Power IP Verification Engineer on their cutting-edge team responsible for the entire verification lifecycle from concept to post-silicon support. In this role, you will plan comprehensive pre-silicon tests, develop testbenches using SystemVerilog-UVM, create coverage and assertion models, and perform formal verification. You’ll also learn and implement power-aware UPF verification flows and develop automation scripts to enhance efficiency. Ideal candidates have a Master’s degree in Computer Science or Electrical Engineering and at least 6 years of experience with ASIC design tools, digital RTL languages like SystemVerilog, UVM methodologies, and scripting languages such as Perl or Python. Familiarity with AMBA bus protocols and assertion-based formal verification is beneficial but not required.
Skills
What you'll do
What we're looking for
Market check
This $115,600–$173,400 range sits above 18% of similar postings on FindRole.
Peer median band
$148,800–$221,800
Median floor and ceiling across peers.
Typical midpoint (25–75%)
$157,800–$216,250
Middle half of comparable postings.
Based on 240 comparable postings.
* 240 is the maximum number of comparable postings sampled.
Employer
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 569 open roles on FindRole.
Listed pay typically runs $148,300–$224,400 across 536 roles with salary data.
Most-posted roles
More like this
Qualcomm
Qualcomm
Qualcomm
Qualcomm
Cisco
Qualcomm