Senior ASIC Design Verification Engineer

Amazon Inc

Quick summary

Work type: On-site
Location: Austin, TXSunnyvale, CARedmond, WASan Diego, CA
Salary: $159,200–$215,300 / yr
Posted: 2 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $179k

This role $187k

$135k most similar roles pay here $224k

This role pays more than 69% of similar roles. Most pay $160,000–$197,750 — the shaded band above. At the midpoint, this role pays about $187k versus about $179k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 321 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 304 roles with salary data.

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At a glance

TL;DR · Senior ASIC Design Verification Engineer

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As a Senior ASIC Design Verification Engineer at Amazon Leo, you will join the hardware development team to validate complex ASIC implementations in Verilog/SystemVerilog and collaborate closely with design and communication systems teams. Your daily tasks include constructing test benches using UVM, SystemC, and DPI-C for system-level verification. The ideal candidate possesses extensive experience in digital verification, particularly within communication systems, along with proficiency in C, SystemC, and scripting languages. Familiarity with Matlab and modem design verification is a plus. This role demands expertise in developing or integrating DV models using SystemC or Matlab, contributing to the development of cutting-edge satellite communication technology at Amazon's scale.

Skills

UVM SystemVerilog C SystemC DPI-C Matlab

What you'll do

Participate in validating ASIC implementations using Verilog/SystemVerilog.
Construct and utilize test benches for system-level verification with UVM.
Collaborate on communication systems verification with design teams.
Develop verification environments using SystemC and DPI-C technologies.
Integrate and develop models using System C or Matlab for DV.

What we're looking for

Bachelor's degree in Electrical or Communications Engineering.
7+ years of verification experience, preferably in communication systems.
3+ years of UVM, C, SystemC, and scripting experience.
Strong background in digital verification techniques.
Experience with test benches constructed using UVM, SystemC, and DPI-C.
Familiarity with modem design verification is preferred.
Knowledge of Matlab for system modeling or DV integration.

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