Digital ASIC Design Engineer for Mixed-Signal IPs

Qualcomm

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $115,600–$173,400 / yr
Posted: 18 days ago
Closes: Dec 7, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $186k

This role $144k

$103k most similar roles pay here $234k

This role pays less than 85% of similar roles. Most pay $160,000–$212,500 — the shaded band above. At the midpoint, this role pays about $144k versus about $186k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 828 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 508 roles with salary data.

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At a glance

TL;DR · Digital ASIC Design Engineer for Mixed-Signal IPs

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The Mixed-Signal IP team at Qualcomm is seeking an experienced RTL and ASIC design engineer to join their dynamic cross-functional group focused on developing next-generation mixed-signal IPs like DACs, ADCs, and PLLs for integration into various Qualcomm products. In this role, you will architect and define the digital design of complex IP blocks in collaboration with system architecture and analog teams, implementing RTL and enhancing power, performance, and area (PPA) through advanced techniques. You will utilize industry-standard tools such as VCS, Fusion Compiler, PrimeTime, and Power Compiler for lint checking, CDC analysis, DFT, synthesis, formal verification, and static timing analysis. Additionally, you will create comprehensive design documentation, collaborate with the DV team to verify designs, support physical design teams in floorplanning and placement, and assist with SoC integration and debug. The ideal candidate has a Master’s degree in Electrical or Computer Engineering, 3+ years of experience in RTL and ASIC design, and proficiency with front-end ASIC design tools.

Skills

VCS Fusion Compiler PrimeTime Power Compiler (PTPX) DFT Compiler Spyglass Python Perl

What you'll do

Define and architect digital design of Mixed-Signal IPs like DACs, ADCs, and PLLs.
Develop micro-architecture and implement RTL for complex mixed-signal IP blocks.
Enhance power, performance, and area (PPA) using advanced ASIC design techniques.
Utilize industry-standard tools for lint checking, CDC analysis, DFT, synthesis, FV, and STA.
Design and analyze DFT logic including ATPG for SAF and TDF coverage.
Collaborate with PD team to support floorplanning, placement, and timing closure of IPs.

What we're looking for

3+ years of experience in RTL and ASIC design.
Proficiency with industry-standard front-end ASIC design tools like VCS, Fusion Compiler, PrimeTime, Power Compiler (PTPX), DFT Compiler, Spyglass.
Master’s degree in Electrical Engineering, Computer Engineering, or related field.
Experience developing micro-architecture and implementing RTL for complex mixed-signal IP blocks.
Strong understanding of power, performance, and area (PPA) optimization techniques.
Collaboration with design verification and physical design teams on test plans and timing closure.

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