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C/C++ UVM System C DPI-C Matlab

UVM SystemVerilog C Matlab Python DPI-C SystemC Formal verification Verilog VCS DVflow CI/CD +7 more Show less

RTL Verilog SystemVerilog VHDL SoC IP integration Ethernet SERDES LPDDR5/6X Arm CPU 3rd party IP blocks low power design DFT synthesis STA physical design deep sub-micron nodes communication systems wireless communications serial protocols SPI I2C I3C UART +19 more Show less

UVM Matlab SystemC DPI-C Verilog VHDL RTL Python CI/CD AWS Linux Git SVN JIRA Confluence +10 more Show less

UVM SystemVerilog C SystemC DPI-C Matlab +1 more Show less

MATLAB UVM SystemC DPI-C RTL DSP Verilog VHDL Linux Python Git CI/CD ASIC FPGA Simulation Verification Power Optimization Timing Optimization +13 more Show less

RTL UVM SystemC DPI-C DSP MATLAB Verilog VHDL ASIC CMOS Linux Git CI/CD Python PostgreSQL +10 more Show less

SystemC UVM DPI-C RTL DSP Matlab Verilog VHDL Linux Python Git CI/CD FPGA ASIC PowerPC Xilinx Cadence Synopsys Tapeout +14 more Show less

C/C++ UVM SystemC DPI-C Matlab

C/C++ UVM SystemC DPI-C Matlab

VHDL Verilog SystemVerilog Xilinx Vivado AMD Vitis Synopsys VCS AXI Ethernet TCP/IP PCIe GitLab UVM Simulink C C++ MATLAB Python Synplify ChipScope +14 more Show less

VHDL Verilog SystemVerilog Xilinx Vivado AMD Vitis UltraScale design methodology Synopsys VCS AXI Ethernet TCP/IP PCIe Serial protocols High-speed oscilloscopes Spectrum analyzers Signal generators Synopsys EDA tools Simulink HDL Coder C/C++ DSP +15 more Show less

VHDL Verilog Xilinx Intel Vivado Quartus MATLAB Simulink High-Level Synthesis Power Analysis Thermal Analysis Design Assurance Configuration Management Mentorship ASIC Design FPGA Co-Design Hardware-Software Co-Verification +12 more Show less

VHDL Xilinx Vivado Intel Quartus Mentor Questa HDL UVM FPGA DSP MATLAB CUDA OpenCL Simulink HDL Coder Xilinx System Generator Digital Signal Processing Radar Electronic Warfare +10 more Show less

VHDL Verilog SystemVerilog Linux FPGAs Digital ASICs Mixed-signal ASICs Atlassian JIRA Microsoft Project Earned Value Management System CI/CD +6 more Show less

VHDL Verilog SystemVerilog Linux AMD_Xilinx_Vivado Microchip_Libero MS_Project JIRA Earned_Value_Management_System CI/CD +5 more Show less

Python Perl Verilog SystemVerilog dc_shell VCS Debussy GDB RTL CDC multiple-power domains performance analysis latency data flow object-oriented programming SOC architecture design automation +12 more Show less

Python Perl Verilog SystemVerilog dc_shell VCS Debussy GDB Kubernetes CI/CD Terraform AWS Git Jenkins PostgreSQL +10 more Show less

Verilog Python Perl Unix/Linux Makefiles CI/CD +1 more Show less

Verilog SysVerilog C++ Python Perl TCL AgenticAI ClaudeCode Cursor CoPilot +5 more Show less