Analog/Mixed Signal ASIC Design Engineer

Qualcomm

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $115,600–$173,400 / yr
Posted: 5 days ago
Closes: Dec 7, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $180k

This role $144k

$101k most similar roles pay here $249k

This role pays less than 85% of similar roles. Most pay $152,150–$208,800 — the shaded band above. At the midpoint, this role pays about $144k versus about $180k for comparable roles.

Based on 239 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 749 open roles on FindRole.

Listed pay typically runs $154,000–$231,000 across 429 roles with salary data.

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At a glance

TL;DR · Analog/Mixed Signal ASIC Design Engineer

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The QCT Mixed-Signal IP (MSIP) design team at Qualcomm seeks an Analog/Mixed Signal ASIC Design Engineer to contribute to the development of high-performance, low-power mixed-signal IPs including SerDes, DDR, PLL, DAC, ADC, and sensors in advanced silicon processes. This role involves defining architectures, performing schematic design with Cadence Virtuoso, collaborating with layout and digital teams for implementation and verification, and supporting post-silicon validation and production issues. Ideal candidates hold a Master's degree in Electrical Engineering and have experience with ASIC design tools like Cadence Virtuoso, along with several years of industry experience in analog circuit/system design, particularly in mixed-signal IPs. Strong skills in Matlab and Python, as well as knowledge of system integration and signal processing, are preferred for this challenging role targeting 5G, AI/ML, compute, and automotive applications.

Skills

Cadence_Virtuoso Python Matlab ASIC SerDes DDR PLL DAC ADC Sensors Design_for_Yield Signals_and_Systems Sampled_Domain_Signal_Processing

What you'll do

Develop high-performance and low-power mixed-signal IPs including SerDes, DDR, PLL.
Capture schematics and perform circuit simulations using Cadence Virtuoso tool suite.
Collaborate with layout and digital teams for design implementation and verification.
Support post-silicon verification, bringup, debug, and production support with test teams.
Define architecture and analog/digital design partitioning for mixed-signal IPs.

What we're looking for

Master's degree in Electrical Engineering or related field.
Experience with Cadence Virtuoso for ASIC design tools.
Industry experience in analog integrated circuit/system design.
Design experience with mixed-signal IPs like SerDes, DDR, PLL.
Understanding of architecture and system aspects for mixed-signal systems.

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