Digital ASIC Design Engineer
Qualcomm
At a glance
AI generatedQualcomm Technologies is seeking a Senior ASIC Design Engineer to join its Next Generation High-Speed Memory and Cache Controller team, focusing on developing advanced memory subsystems for high-speed HBM/LPDDR/DDR interfaces in QCT products. The role involves architecture definition, RTL coding, and deployment of next-generation memory controllers interfacing with CPUs, GPUs, DSPs, and multimedia processors at gigahertz speeds. Key responsibilities include designing micro-architectures, implementing RTL code, collaborating with verification engineers, debugging designs, and supporting physical design tasks such as synthesis, timing closure, and power analysis. Ideal candidates have 5+ years of ASIC design experience, a strong background in hardware architecture, and expertise in LPDDR memory controllers, NoC-based architectures, and x86 or ARM CPU/bus systems.
Skills
What you'll do
What we're looking for
Market check
This $140,000–$210,000 range sits above 32% of similar postings on FindRole.
Peer median band
$152,000–$241,400
Median floor and ceiling across peers.
Typical midpoint (25–75%)
$160,000–$223,700
Middle half of comparable postings.
Based on 240 comparable postings.
* 240 is the maximum number of comparable postings sampled.
Employer
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 569 open roles on FindRole.
Listed pay typically runs $148,300–$224,400 across 536 roles with salary data.
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