Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer

Qualcomm

Actively hiring
San Diego, CA Posted 21 days ago $140,000$210,000 / year

At a glance

AI generated

TL;DR

Qualcomm Technologies is seeking a Senior ASIC Design Engineer to join its Next Generation High-Speed Memory and Cache Controller team, focusing on developing advanced memory subsystems for high-speed HBM/LPDDR/DDR interfaces in QCT products. The role involves architecture definition, RTL coding, and deployment of next-generation memory controllers interfacing with CPUs, GPUs, DSPs, and multimedia processors at gigahertz speeds. Key responsibilities include designing micro-architectures, implementing RTL code, collaborating with verification engineers, debugging designs, and supporting physical design tasks such as synthesis, timing closure, and power analysis. Ideal candidates have 5+ years of ASIC design experience, a strong background in hardware architecture, and expertise in LPDDR memory controllers, NoC-based architectures, and x86 or ARM CPU/bus systems.

Skills

RTL Verilog SystemVerilog VHDL ASIC LPDDR HBM NoC CPU x86 ARM Cache Controller Memory Subsystem Digital Design Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis RTL Design Verification

What you'll do

  • Develop architecture and design specifications for high-speed memory subsystems.
  • Implement RTL code for next-generation memory controllers and cache systems.
  • Collaborate with verification engineers to ensure high-quality designs are delivered.
  • Debug complex logic designs and provide support during chip integration phases.
  • Conduct synthesis, timing closure, and physical design support tasks efficiently.
  • Perform gate-level simulations and power analysis on memory subsystems.

What we're looking for

  • 5+ years of ASIC design and RTL coding experience
  • 3+ years of hardware architecture experience
  • Experience with LPDDR memory and cache controller designs
  • Familiarity with NoC based architectures and front-end interfacing to CPUs/DSPs
  • Knowledge of HBM memory type designs and on-chip SRAM/L3 cache controllers
  • Understanding of x86 or ARM CPU/bus architectures
  • Ability to debug high-speed (1GHz+) designs in QCT products

Market check

Salary context

This $140,000–$210,000 range sits above 32% of similar postings on FindRole.

Peer median band

$152,000$241,400

Median floor and ceiling across peers.

Typical midpoint (25–75%)

$160,000$223,700

Middle half of comparable postings.

Based on 240 comparable postings.

* 240 is the maximum number of comparable postings sampled.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 569 open roles on FindRole.

Listed pay typically runs $148,300–$224,400 across 536 roles with salary data.

Most-posted roles

View all roles at Qualcomm

More like this

Similar roles

Digital ASIC Design Engineer

Qualcomm

San Diego, Ca,Us, US 21 days ago $98,500$147,700
Verilog SystemVerilog VHDL Python Perl RTL SoC ASIC Clock_design Power_related_features Design_verification Simulation Scripting_languages Automation_tools

VLSI Design Engineer for Server / Data Center Products

Qualcomm

San Diego, Ca,Us, US 21 days ago $140,000$210,000
Verilog SystemVerilog VHDL Python Perl TCL Linux Cadence Synopsys ASIC FPGA RTL Design PCIe DDR CXL MIPI USB SMPTE2110 AMBA4 AXI AI Machine Learning High Performance Compute

ASIC Design Engineer (Hardware Security)

Qualcomm

San Diego, Ca,Us, US 23 days ago $140,000$229,800
verilog system-verilog RTL DFT AHB AXI ASIC SoC Security Crypto Cryptography Encryption side-channel High-speed Low Area Low Power Root of Trust RNG symmetric crypto asymmetric crypto silicon test bus protocols clocks/resets debug concepts

ASIC Design Verification Technical Leader

Cisco

Remote (Usa-Carlsbad, US) 49 days ago $163,600$234,600
SystemVerilog UVM Python Perl TCL Shell SerDes D2D_PHY_IP ODSP Ethernet UCIE UAL SPI I2C Formal_Verification Verilog Veloce HAPS Emulation_Pods
Remote

ASIC Design Engineer

Qualcomm

Santa Clara, Ca,Us, US 78 days ago $126,700$190,100
Python Perl AMBA AHB APB AXI PCIe USB CoreSight AI/ML DFT FPGA CDC Clocking_architecture NoC