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UVM Formal Verification Python PCIe CXL AMBA CHI Fabric Interconnects Assertions Coverage Simulation Data Analysis Automation AI-driven solutions +9 more Show less

Physical Design RTL-to-GDS SerDes PHY Logic Synthesis Place and Route Clock Tree Synthesis Physical Verification Static Timing Analysis Verilog Floorplanning IP Integration Logic Equivalence Checking Power Gating Scan Stitching EDA Tools Circuit Simulation Logic Simulation +12 more Show less

IC Package Design ASIC RFIC Power Integrity EM Simulation Cadence APD+ SIP HFSS SIWave ADS BGA Co-packaged Optics Tapeout Substrate Design Mixed Signal silicon floor plan +11 more Show less

IC Package Design ASIC RFIC Cadence APD+ SIP SIWave HFSS ADS Power Integrity EM Simulation BGA Co-packaged Optics Tapeout Substrate Design Mixed Signal +10 more Show less

IC Design Analog/Mixed-Signal PLL FPGA SystemVerilog Vivado ADPLL LDO VCO Clock Synthesis Digital Verification Post-Silicon Validation Device Physics +8 more Show less

System Design System Implementation TCP/IP LTE Technical Writing Radio Voice Communications CJIS) Security Policy Digital Evidence Management Public Safety Software +4 more Show less

SRAM Design Cadence Virtuoso Transistor-level Circuit Design Layout Capture Logical Verification Silicon Testing SRAM Compiler Development SOC Design Codex Claude Code Debug +6 more Show less

Silicon Photonics PIC RFIC Lumerical COMSOL HFSS Spectre ADS SerDes PAM4 NRZ MZM Microring Modulators InGaAs InP CTLE Spectrum Analyzers Vector Signal Analyzers High Speed Oscilloscopes BERT Floor Planning +16 more Show less

SRAM Design Transistor-level Circuit Design Cadence Virtuoso FinFET Nanosheet Digital Circuit Design Layout Capture Logical Verification Silicon Testing Sense-amplifiers Self-timed Logic SRAM Compiler Development Codex Claude Code +9 more Show less

Physical Design ASIC Design Flow Synthesis Place and Route Clock Tree Synthesis floor planning TCL Perl Shell Python DFM Signal Integrity FinFET +8 more Show less

RFIC Design mm-Wave Analog Circuit Design Mixed-Signal Design FinFET SOI BiCMOS Bulk CMOS HFSS EMX RLC Extraction 4G 5G NR WiMAX 802.11ad Network Analyzers Spectrum Analyzers Oscilloscopes Probe-stations +14 more Show less

Verilog System Verilog ASIC SoC RTL Design Python AXI AHB EDA Tools HDL Simulators HDL Lint Tools Synthesis Timing Closure Formality Check Clock Domain Crossing Power Optimization +11 more Show less

Hardware Engineering BIOS BMC Redfish SIPI Agile JIRA Confluence SharePoint PCIe Networking Storage Thermal Mechanical Telemetry Board Design +11 more Show less

SRAM Design Circuit Design RTL Schematic Capture DFT IR/EM Backend Verification Machine Learning Simulations +4 more Show less

Tcl Python Cadence Innovus Place-and-Route Physical Design Timing Analysis Physical Verification Digital Design Automation PPA 5nm Hardware Engineering +7 more Show less

SRAM Design Verilog Schematic Capture Circuit Simulation Static Timing Analysis Monte Carlo Analysis Layout Design DFT BIST NanoTime Ansys EMIR ESP-CV Liberate FinFET Nanosheet Functional Verification Power Analysis Electrical Characterization +13 more Show less

Schematic Capture High-Speed Digital Design Signal Integrity Power Integrity Siemens/Mentor Xpedition Cadence Allegro Hyperlynx LTspice Ethernet PCIe DDR USB I2C SPI Oscilloscope Logic Analyzer Multimeter +12 more Show less

PCB Design Schematic Capture Cadence Allegro Mentor Expedition Signal Integrity Power Integrity SPICE PCIe Gen5/6 LPDDR4x/5x DDR4/5 Ethernet JTAG Oscilloscope Logic Analyzer x86 ARM BMC SMBus PMBus SPI PWM Thermal Management EMI Shielding Bring-up Debugging +20 more Show less

Verilog System Verilog RTL Design ASIC SoC Python AXI AHB EDA Tools HDL Simulators HDL Lint Tools Synthesis Timing Closure Formality Check Clock Domain Crossing Power Optimization +11 more Show less

RTL Design Verilog System Verilog ASIC SoC Python AXI AHB Synthesis Timing Closure HDL Simulators HDL Lint Tools Clock Domain Crossing Power Optimization Embedded CPU Subsystems +10 more Show less