Senior ASIC Design Engineer, Silicon Engineering

SpaceX

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Redmond, WAAustin, TXIrvine, CAPalo Alto, CA
Salary
$165,000–$270,000 / yr
Posted
3 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $199k
This role $218k
$137k most similar roles pay here $284k

This role pays more than 71% of similar roles. Most pay $171,125–$227,500 — the shaded band above. At the midpoint, this role pays about $218k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 654 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 468 roles with salary data.

Most-posted roles

View all roles at SpaceX

At a glance

TL;DR · Senior ASIC Design Engineer, Silicon Engineering

Role Posting Log in to save

Sr. ASIC Design Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation ASICs for space and ground infrastructure. This role focuses on building advanced chips that enable global connectivity through the Starlink network. The engineer will evaluate architectural trade-offs, define micro-architecture, and implement RTL in Verilog and System Verilog while ensuring designs are synthesis and timing clean. Key responsibilities include providing timing constraints, supporting physical implementation teams with synthesis and timing closure, and participating in silicon bring-up and validation. Required skills include experience with embedded CPU subsystems, standard bus protocols like AXI and AHB, high speed and low power design techniques, and scripting in Python. The candidate will utilize EDA tools, including HDL simulators and lint tools, to solve complex problems such as clock domain crossings and power optimization for critical infrastructure.

What does a ASIC Design Engineer earn in California?

Median $214000 from 45 postings across 7 companies.

See salary data

Skills

Verilog System Verilog ASIC SoC RTL Design Python AXI AHB EDA Tools HDL Simulators Timing Closure Synthesis Clock Domain Crossing Power Optimization Silicon Bring-up

What you'll do

  • Evaluate architectural trade-offs based on features, performance requirements, and system limitations.
  • Define micro-architecture for next-generation ASICs used in space and ground infrastructure.
  • Implement RTL designs using Verilog or System Verilog.
  • Integrate designs into the top level to deliver synthesis and timing clean results.
  • Collaborate with verification teams to ensure all design aspects are fully covered and verified.
  • Provide timing constraints for IPs and support physical implementation tasks like synthesis and timing closure.
  • Participate in silicon bring-up and validation processes.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • 5+ years of experience in RTL implementation.
  • Ability to work extended hours or weekends as needed for mission critical deadlines.
  • Must be a U.S. citizen, national, lawful permanent resident, refugee, or asylee (or eligible for such status) per ITAR regulations.
  • Ability to solve complex problems including clock domain crossings and power optimization (preferred).
  • ASIC/SoC system integration experience (preferred).
  • Experience with embedded CPU subsystems and standard bus protocols like AXI or AHB (preferred).
  • Experience with high speed/low power design, scripting (Python), and EDA tools (preferred).

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