PLL Design/ Integration Senior Staff Engineer

Amd

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$200,000–$300,000 / yr
Posted
5 days ago
Freshness
Confirmed live today
Closes
Oct 21, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k
This role $250k
$138k $317k
below market most similar roles pay here above market

This role pays more than 89% of similar roles. Most pay $176,600–$227,500 — the blue band above. At the midpoint, this role pays about $250k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · PLL Design/ Integration Senior Staff Engineer

Role Posting Log in to save

The PLL Design/ Integration Sr Staff Engineer joins the AECG Fabric team within the Programmable Logic Group to lead the design, integration, and characterization of Phase-Locked Loops for FPGA products. You will architect and integrate analog/mixed-signal building blocks like VCOs, charge pumps, dividers, PFDs, and Loop Filters across cutting-edge process nodes. Key responsibilities include integrating various PLL topologies such as integer-N, fractional-N, and all-digital PLLs to meet power, area, and jitter specifications. You will supervise layouts, conduct lab bring-up, and perform system-level simulations using Vivado. Required skills include IC design, device physics, and knowledge of LDOs, bias generators, and operational amplifiers. You will solve complex clocking challenges involving self-heating, electromigration, and noise optimization for sophisticated SoCs.

Skills

IC Design Analog/Mixed-Signal PLL FPGA SystemVerilog Vivado ADPLL LDO VCO Clock Synthesis Digital Verification Post-Silicon Validation Device Physics

What you'll do

  • Architect and integrate analog/mixed-signal PLL building blocks into FPGA products across cutting-edge process nodes.
  • Lead the integration of various PLL topologies to meet power, area, jitter, and frequency specifications.
  • Address advanced node challenges including self-heating, electromigration, and device-level noise optimization.
  • Supervise and verify layouts to ensure proper floor planning, matching, and parasitic minimization.
  • Perform PLL bring-up in the lab and conduct performance characterization using state-of-the-art equipment.
  • Conduct system-level simulations and validation for PLL IP integration using Vivado or similar tools.

What we're looking for

  • Experience in IC design and manufacturing, including analog/digital IP integration, chip design, silicon processes, and packaging technologies.
  • Strong understanding of device physics, reliability, and silicon chip manufacturing.
  • Ability to architect and integrate analog/mixed-signal PLL building blocks into FPGA products across cutting-edge process nodes.
  • Experience leading the integration of different PLL topologies to meet power, area, jitter, and frequency specifications.
  • Ability to supervise and verify layouts to ensure floor planning, matching, and parasitic minimization.
  • Experience with PLL bring up in the lab and performance characterization using state-of-the-art equipment.
  • Ability to conduct system-level simulations and validation for PLL IP integration using Vivado or similar tools.
  • Master's degree in electrical & electronics engineering (preferred) or a bachelor's degree with several years of relevant industry experience.

Related searches

More PLL Design jobs PLL Design jobs in San Jose All jobs at Amd

More like this

Similar roles

Senior Engineer, PLL Design

Samsung Semiconductor

San Jose, CA 22 days ago $138,000–$206,000
PLL Design CMOS Matlab Simulink Verilog SystemVerilog Spectre SpectreRF AMS RF Transceivers SerDes Mixed-Signal Simulation Monte Carlo Analysis Silicon Correlation RTL Design Jitter Budgeting
2+ yrs exp
Save

PLL Design Engineer

Apple Inc

Austin, TX 40 days ago
PLL FLL Frequency Synthesis VCO DCO Fractional-N System Verilog RTL Jitter Analysis Op-Amps LDOs Scripting SOC SerDes
Save

PLL Design Engineer

Apple Inc

San Diego, CA 40 days ago $175,000–$308,500
PLL FLL Frequency Synthesis VCO DCO Fractional-N System Verilog RTL Jitter Analysis Op-Amps LDOs Scripting SOC SerDes
10+ yrs exp
Save

PLL Design Engineer

Apple Inc

Austin, TX 40 days ago
PLL FLL Frequency Synthesis VCO DCO Fractional-N System Verilog RTL SerDes SoC Jitter Analysis Op-Amps LDOs Scripting
10+ yrs exp
Save

PLL Design Engineer

Apple Inc

Cupertino, CA 5 days ago $184,700–$324,800
PLL FLL Frequency Synthesis System Verilog RTL VCO DCO SerDes SoC Scripting Jitter Analysis Op-Amps
10+ yrs exp
Save

Senior Staff RFIC Design Engineer

Qualcomm

San Diego, CA 40 days ago $133,900–$200,900
RFIC Design ASIC Design CADENCE Virtuoso ADS RF/Analog circuits Transistor-level Design LNA PLL 5G 4G 6G WLAN GPS Electro Magnetic simulation Neural Networks Physical Verification
3+ yrs exp
Save