SRAM Circuit Design Engineer

Nvidia

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$116,000–$189,750 / yr
Employment
Full-time
Posted
14 days ago
Freshness
Confirmed live today

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $182k
This role $153k
$104k $232k
below market most similar roles pay here above market

This role pays less than 65% of similar roles. Most pay $147,200–$217,500 — the blue band above. At the midpoint, this role pays about $153k versus about $182k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · SRAM Circuit Design Engineer

JOB TITLE: SRAM Circuit Design Engineer - New College Grad 2026 The SRAM Circuit Design Engineer - New College Grad 2026 joins the Digital IP group to develop sophisticated SRAM compilers used by SOC design partners. This role involves transistor-level circuit design, supervising layout implementation, and performing physical and logical verification and debug of SRAM macros. You will envision and code efficient ways to automate the simultaneous assembly and validation of unique SRAM macros while exploring future process nodes to optimize power, performance, and area characteristics. Key requirements include a Master's degree in Electrical Engineering, experience with advanced FinFET and nanosheet processes, and proficiency in Cadence Virtuoso schematic and layout capture tools. You must demonstrate experience with single-port, dual-port, or register file SRAM-based macros, including self-timed logic and sense-amplifiers, to support silicon IP production.

What you'll do

  • Perform transistor-level circuit design for embedded SRAM macros.
  • Supervise layout implementation, physical and logical verification, and debug of SRAM macros.
  • Code automated systems for the simultaneous assembly and validation of multiple unique SRAM macros.
  • Explore future process nodes to develop techniques for optimal power, performance, and area.
  • Guide SOC design partners in achieving specific performance and cost goals.
  • Lead silicon test and characterization efforts for new hardware.
  • Prepare new silicon for real-world application requirements with productization teams.

What we're looking for

  • Master's degree or higher in Electrical Engineering or a related field, or equivalent experience.
  • SRAM design experience with a strong background in digital circuit design, layout, and validation on advanced FinFET and nanosheet processes.
  • Design experience in single-port, dual-port, or register file SRAM-based macros, including self-timed logic and sense-amplifiers.
  • Familiarity with Cadence Virtuoso schematic and layout capture tools.
  • Proven delivery of silicon IP into production.
  • Shown written, verbal, and presentation skills (preferred).
  • Skills in AI coding and analysis tools such as Codex and Claude Code (preferred).
  • Silicon testing and debug experience (preferred).

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