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Active Keyword: RTL Engineer Remove filter Clear all

20 of up to 20 (filtered)

ASIC/RTL Design Engineer for High-speed Interfaces

Qualcomm

San Diego, CA 3 days ago $140,000–$210,000
Actively hiring Confirmed live yesterday Posted this week High trust Below market
RTL ASIC Design SerDes DDR PCIe USB UFS MIPI VCS Fusion Compiler PrimeTime Power Compiler Spyglass Python Perl DFT STA CDC GDSII
4+ yrs exp
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CPU Core Architecture RTL Engineer

Amd

Fishkill, NY 11 days ago $200,000–$300,000
Actively hiring Confirmed live yesterday High trust Above market
RTL Verilog CPU Architecture Microarchitecture ASIC SoC x86 ARM Synthesis static timing *analysis DFT DFD Power Management Perl Shell Tcl Floorplan Tapeout
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CPU RTL Power Engineer

Qualcomm

Austin, TX 12 days ago $148,300–$222,500
Actively hiring Confirmed live 2 days ago Trusted Competitive pay
RTL Power Modeling PowerArtist PTPX Verilog VHDL Python Perl Clock Gating Logic Design Power Estimation
4+ yrs exp
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CPU Systems RTL Engineer

Qualcomm

Santa Clara, CA 12 days ago $167,100–$250,700
Actively hiring Confirmed live yesterday Trusted Above market
RTL Verilog VHDL Microarchitecture Logic Design Python Perl Waveform Debugging Simulators Power Management Functional Verification Hardware Engineering Firmware
4+ yrs exp
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RISCV CPU System RTL Engineer

Qualcomm

Santa Clara, CA +3 12 days ago $142,200–$213,400
Actively hiring Confirmed live yesterday Trusted Competitive pay
RISCV RTL Design Verilog VHDL Microarchitecture Logic Design Power Management Python Perl Waveform Debugging Simulators Hardware Engineering System Architecture
2+ yrs exp
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CPU RTL Methodology Engineer

Qualcomm

Santa Clara, CA +1 12 days ago $198,700–$298,100
Actively hiring Confirmed live yesterday High trust Above market
RTL Verilog SystemVerilog Python TCL Perl Bash GIT CI/CD CAD Tools CPU Microarchitecture Hardware Design Automation Scripting
6+ yrs exp
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RTL Design & Integration Engineer

Amd

San Jose, CA 20 days ago $166,400–$249,600
Actively hiring Confirmed live 2 days ago High trust Above market
Verilog SystemVerilog RTL Design VLSI FPGA Python Tcl Perl Shell Synopsys Design Compiler Primetime VCS Cadence Virtuoso UVM OVM STA Synthesis P&R GDSII Simulation
Hybrid
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Senior RTL Engineer, IO Die and Interconnect IP

Samsung Semiconductor

San Jose, CA 21 days ago $138,000–$206,000
Actively hiring Confirmed live yesterday High trust Below market
Verilog SystemVerilog RTL Design UCIe PCIe CXL NoC SoC Integration IP-XACT AXI ACE CHI APB Python Tcl Perl AI/ML Agentic AI
5+ yrs exp
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Senior RTL Engineer, Memory Centric Computing

Samsung Semiconductor

San Jose, CA 23 days ago $138,000–$206,000
Actively hiring Confirmed live yesterday High trust Below market
Verilog System Verilog HLS RTL Microarchitecture Computer Architecture Memory Controller NoC Interconnect IP SoC Integration AI/ML Pipelining Data Compression
5+ yrs exp
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CPU Micro-Architecture and RTL Design Engineer (RISC-V)

Qualcomm

Santa Clara, CA +1 43 days ago $167,100–$250,700
Actively hiring Confirmed live 2 days ago Low trust Competitive pay
RISC-V RTL Design Verilog VHDL Microarchitecture Python Perl Logic Design Functional Verification Waveform Debugging Instruction Fetch and Decode Branch Prediction Out-of-Order Execution
4+ yrs exp
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Senior Engineer, GPU RTL Design

Samsung Electronics

Remote (Austin, TX) 43 days ago $124,000–$208,400
Actively hiring Confirmed live yesterday Trusted Below market
RTL Verilog SystemVerilog GPU SoC ASIC Synthesis Linting Timing Analysis PPA Microarchitecture Datapath Cache Design Memory Systems
4+ yrs exp Remote
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Senior Engineer, GPU RTL Power

Samsung Electronics

Remote (Austin, TX) 43 days ago $124,000–$186,000
Actively hiring Confirmed live 2 days ago High trust Below market
RTL CPU Architecture SystemVerilog ASIC Design Flow PowerArtist PTPX Empower Python Perl STA Synthesis Clock Gating Power Gating Low-Power Design
2+ yrs exp Remote
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RTL Power Optimization Engineer

Nvidia

Santa Clara, CA 52 days ago $116,000–$189,750
Actively hiring Confirmed live 2 days ago High trust Below market
RTL Verilog Python Machine Learning Artificial Intelligence Power Analysis VLSI Logic Synthesis place‑and‑route PowerArtist PrimeTime PX Digital Design
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CPU Core RTL Design Engineer

Amd

Austin, TX 64 days ago $178,400–$267,600
Actively hiring Confirmed live 2 days ago High trust Above market
Verilog SystemVerilog RTL Design CPU Architecture ASIC SoC Logic Design Synthesis Timing Closure Python Tcl DFT Power Management Post-silicon Debug Place-and-Route
Hybrid
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DDRSS Validation Engineer

Qualcomm

San Diego, CA 74 days ago $140,000–$210,000
Actively hiring Confirmed live 2 days ago Trusted Competitive pay
Verilog SystemVerilog C SoC RTL Firmware Emulation Post-silicon Validation Silicon Bring-up DDR Cache Interconnect Computer Architecture Testbench Automation Debug Infrastructure
4+ yrs exp
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CPU Micro-Architect RTL Engineer

Qualcomm

Austin, TX 87 days ago $98,500–$147,700
Actively hiring Confirmed live yesterday Low trust Below market
RTL Design CPU Microarchitecture RISC-V Processor Pipelines Out-of-Order Execution Cache Coherence Memory Hierarchy Multi-threaded Systems Low-Power Optimization
1+ yrs exp
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Processor Micro Architect RTL Design Engineer

Qualcomm

San Diego, CA 87 days ago $180,400–$270,600
Actively hiring Confirmed live 2 days ago Trusted Above market
RTL Verilog System Verilog ASIC Design Logic Design Digital Design Static Timing Analysis Low Power Design Microprocessor Architecture Cache Bus Protocol Linting Clock Domain Crossing GDS2 Synthesis Simulation Regression
6+ yrs exp
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Software R&D Engineer, RTL Optimization Tools

Nvidia

Santa Clara, CA +1 92 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday High trust Competitive pay
C++ RTL Verilog SystemVerilog Machine Learning Reinforcement Learning EDA Logic Synthesis Static Timing Analysis SAT Solvers Multithreading Distributed Computing DFT Power Gating Clock Distribution
3+ yrs exp Hybrid
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Senior FPGA / RTL Design Engineer, Signal Processing

Motorola Solutions

Los Angeles, CA +1 95 days ago $125,000–$195,000
Actively hiring Confirmed live yesterday Trusted Below market
FPGA Digital Signal Processing RTL Xilinx Vivado MATLAB Logic Analyzers Hardware Verification Timing Closure Synthesis Simulation Test Bench Development MIMO
6+ yrs exp Hybrid
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