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Verilog SystemVerilog RTL Design CPU Architecture ASIC Logic Design Synthesis Timing Closure Place-and-Route Python Tcl DFT Post-Silicon Debug Power Management Cache Hierarchy TLB Branch Prediction +12 more Show less

Verilog SystemVerilog RTL Design PCIe CXL AMBA Micro-architecture Timing Closure Low-power Design Emulation Validation RAID Storage +7 more Show less

Verilog System Verilog DFT MBIST AMBA AXI APB AHB JTAG UPF Formal Verification Linting CDC Checkers Synthesis Post-Silicon Debug Power Optimization Power Estimation +12 more Show less

RTL Design MATLAB DSP Fixed-point Synthesis CDC Power Analysis Microarchitecture VLSI SoC Signal Processing Bit-true Verification +7 more Show less

RTL Design MATLAB DSP Fixed-point Synthesis CDC Power Analysis VLSI SoC Microarchitecture Signal Processing +6 more Show less

RTL Design MATLAB DSP Fixed-point Synthesis CDC Power Analysis VLSI SoC Microarchitecture front end CAD tools +6 more Show less

RTL Design SystemVerilog Verilog Python Go Java C# TypeScript Perl Ruby Shell TCL LLM RAG Agentic Frameworks Static Analysis Linting Verible Slang Verilator Surelog Synthesis Physical Design Place and Route Timing Closure +20 more Show less

RTL Design MATLAB DSP Fixed-point Synthesis CDC Power Analysis VLSI SoC Microarchitecture Design Verification front end CAD tools +7 more Show less

RTL Design MATLAB DSP Fixed-point Synthesis CDC Power Analysis VLSI SoC Microarchitecture front end CAD +6 more Show less

RTL Design MATLAB DSP Fixed-point Synthesis CDC Power Analysis VLSI SoC Microarchitecture front end CAD tools +6 more Show less

Verilog SystemVerilog RTL Design ASIC Design GPU Architecture Microarchitecture Synthesis Linting Timing Analysis SoC Hardware Design PPA Digital Design Cache Design Memory Systems Datapath Control Logic +12 more Show less

Firmware Development C C++ Assembly RISC-V Verilog SystemVerilog RTL Design ASIC Flow Vulkan OpenGL Direct3D OpenCL GPU Architecture SoC Architecture Bring-up Debug +12 more Show less

Verilog SystemVerilog RTL Design GPU Architecture SoC Power Management Python Perl Microarchitecture Clock Domain Crossing Hardware Design Firmware Digital Design +8 more Show less

Verilog SystemVerilog RTL Design GPU Architecture SoC ASIC Design Flow Linting Synthesis Timing Analysis Microarchitecture PPA Digital Design Debug Simulation +9 more Show less

Verilog SystemVerilog RTL Design PCIe CXL AMBA Micro-architecture Timing Closure Low-power Design Emulation Validation RAID Storage Design Clock Domain Crossing +9 more Show less

SoC RTL Performance Analysis Hardware Emulation Verilog SystemVerilog C C++ Python Ruby Unix Linux Git Subversion ARM Architecture Memory System Architecture Cache Architecture MMU CPU GPU I/O Compilers Assemblers Device Drivers +17 more Show less

FPGA RTL Design Digital Signal Processing Vivado Xilinx Python Perl MATLAB Hardware Verification Logic Analyzers ASIC Wireless Communication Simulation Timing Closure +9 more Show less

FPGA RTL Digital Signal Processing Vivado Xilinx MATLAB Hardware Verification Logic Analyzers ASIC Simulation Test Bench Development Timing Closure MIMO MANET +9 more Show less

RTL Integration SystemVerilog UVM ASIC SoC DFT Python Perl Tcl Shell Scripting CDC RDC Lint ATPG MBIST LBIST JTAG UPF Synopsys Cadence Siemens +16 more Show less

SoC RTL Performance Analysis Hardware Emulation Verilog SystemVerilog C C++ Python Ruby Unix Linux Git Subversion ARM Architecture Memory System Architecture Cache Architecture MMU CPU GPU I/O Compilers Assemblers Device Drivers +17 more Show less