Senior Full-Chip RTL Integration Engineer

Nvidia

Confirmed live today High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CAAustin, TX
Salary: $168,000–$264,500 / yr
Employment: Full-time
Posted: 20 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $186k

This role $216k

$132k $279k

below market most similar roles pay here above market

This role pays more than 79% of similar roles. Most pay $154,853–$216,250 — the blue band above. At the midpoint, this role pays about $216k versus about $186k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior Full-Chip RTL Integration Engineer

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The Senior Full-Chip RTL Integration Engineer joins the FE-ASIC development team within the Advanced Technology Group to support new process technology adoption. This role involves leading the RTL integration of internal and third-party IPs into complex ASIC and SoC designs. Key responsibilities include owning top-level connectivity, clocking, reset architecture, address mapping, and power domain integration while ensuring design quality and DFT compliance. The engineer performs RTL quality checks like lint, CDC, and RDC, and develops verification plans using SystemVerilog and UVM. The position requires collaborating with Architecture, Design, Verification, and Physical Design teams to achieve design closure. Necessary skills include expertise in SoC architecture, bus protocols, and DFT methodologies such as Scan, MBIST, and JTAG, alongside proficiency in Python, Perl, Tcl, or Shell scripting.

Skills

RTL Integration SystemVerilog UVM ASIC SoC DFT Python Perl Tcl Shell Scripting CDC RDC Lint ATPG MBIST LBIST JTAG UPF Synopsys Cadence Siemens

What you'll do

Lead RTL integration of internal and third-party IPs into complex ASIC/SoC designs.
Own top-level connectivity, clocking, reset architecture, address mapping, and power domain integration.
Perform RTL quality checks including lint, CDC, RDC, synthesis, and connectivity validation.
Develop and execute integration-level verification plans using SystemVerilog and UVM.
Integrate scan, MBIST, LBIST, and JTAG structures while reviewing ATPG reports and fault coverage.
Support design signoff activities and ensure smooth handoffs across all implementation stages.
Develop automation and scripting solutions to improve integration, verification, and debug productivity.

What we're looking for

B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field (or equivalent experience).
8+ years of experience in the field.
Strong experience in ASIC/SoC RTL Integration.
Excellent understanding of digital design fundamentals, SoC architecture, clocking, reset, and bus protocols.
Strong verification knowledge with hands-on experience in SystemVerilog and UVM.
Strong understanding of DFT methodologies including Scan, ATPG, MBIST, LBIST, JTAG, and test compression techniques.
Experience with lint, CDC, RDC, and design quality signoff flows.
Experience with large-scale SoC integration, high-speed interfaces, and low-power design methodologies (preferred).

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