Staff Engineer, GPU RTL Power Management

What you'll do

• Design and develop power management and SoC interface RTL blocks for next-generation mobile GPU IPs.
• Translate architectural specifications into efficient, maintainable, and scalable hardware designs.
• Drive the microarchitecture definition and RTL implementation of power management GPU blocks and subsystems.
• Develop clean, synthesizable RTL and collaborate with verification teams to ensure coverage and robustness.
• Resolve functional design challenges regarding interface definition, timing, power, performance, and area tradeoffs.
• Manage the RTL lifecycle from microarchitecture through development, integration, debug, and simulation readiness.
• Implement low-power features including IP power sequences, clock/reset control, and dynamic voltage and frequency scaling.

What we're looking for

• 6+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 4+ years with a Master’s, or 2+ years with a Ph.D.
• 4+ years of hands-on experience in power management or low power microarchitecture design for complex SoC, CPU, or GPU architectures.
• Hands-on experience in RTL design using Verilog/SystemVerilog, including microarchitecture development, integration, and debug.
• Working knowledge of GPU or high-performance digital design power management including IP power sequence, clock/reset control, and DVFS.
• Familiarity with low power intent design for multi-voltage domain systems.
• Proficiency with scripting languages such as Python or Perl.
• Strong analytical, problem-solving, and communication skills for technical documentation and global team collaboration.
• Familiarity with the power management or boot sequence firmware of GPU or CPU (preferred).
• Must be authorized to access information subject to U.S. export control laws.