Senior FPGA / RTL Design Engineer, Signal Processing

Motorola Solutions

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Hybrid

Quick summary

Work type
Hybrid
Location
Los Angeles, CA
Salary
$155,000–$195,000 / yr
Employment
Full-time
Posted
4 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $192k
This role $175k
$144k $229k
below market most similar roles pay here above market

This role pays less than 69% of similar roles. Most pay $168,500–$216,250 — the blue band above. At the midpoint, this role pays about $175k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Motorola Solutions

Motorola Solutions, Inc. (NYSE: MSI) is a leading American technology company providing mission-critical communications, video security, and analytics for public safety and enterprise customers.

Motorola Solutions currently has 159 open roles on FindRole.

Listed pay typically runs $100,000–$130,000 across 121 roles with salary data.

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At a glance

TL;DR · Senior FPGA / RTL Design Engineer, Signal Processing

Role Posting Log in to save

The Senior FPGA / RTL Design Engineer - Signal Processing will join the FPGA Engineering team to support the research and development of advanced wireless systems. This role involves participating in the full development lifecycle from concept to field deployment, specifically focusing on the efficient implementation of novel signal processing algorithms for MIMO wireless networking products. Key responsibilities include digital design architecting, fixed point design of signal processing blocks, RTL coding, simulation, test bench development, FPGA synthesis, and timing closure. The candidate must utilize Xilinx FPGAs, SoCs, and the Vivado IDE while demonstrating expertise in multiple clock-domain, high-utilization designs. The work addresses challenging real-world communication needs for mission-critical applications, including the development of proprietary MN-MIMO waveforms and MANET radios for defense and public safety.

Skills

FPGA RTL Digital Signal Processing Vivado Xilinx MATLAB Hardware Verification Logic Analyzers ASIC Simulation Test Bench Development Timing Closure MIMO MANET

What you'll do

  • Architect digital designs for wireless communication projects.
  • Design fixed-point signal processing blocks in coordination with systems engineers.
  • Perform RTL coding, simulation, and test bench development.
  • Execute FPGA synthesis and ensure timing closure.
  • Conduct hardware verification and troubleshooting using logic analyzers.
  • Provide technical support to the RF and Software Engineering teams.
  • Implement novel signal processing algorithms for MIMO wireless networking products.

What we're looking for

  • Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields.
  • Minimum 6 years of FPGA design experience; 4 years with a Master of Science; 2 years with a PhD.
  • Demonstrated experience with fixed point binary arithmetic and digital signal processing designs.
  • Proven expertise working with multiple clock-domain, high-utilization FPGA designs.
  • Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.
  • Must be a U.S. Citizen.
  • Master of Science degree in Electrical Engineering (preferred).
  • Experience using MATLAB (preferred).

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