RTL IC Design Engineer

Broadcom

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Quick summary

Work type
On-site
Location
Colorado Springs, COSan Jose, CA
Salary
$101,000–$162,000 / yr
Employment
Full-time
Posted
6 days ago
Freshness
Confirmed live today
Closes
Apr 18, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $201k
This role $132k
$83k $267k
below market most similar roles pay here above market

This role pays less than 98% of similar roles. Most pay $171,717–$229,650 — the blue band above. At the midpoint, this role pays about $132k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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At a glance

TL;DR · RTL IC Design Engineer

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The RTL IC Design Engineer joins the Data Center Solutions Group to develop next generation AI/ML ecosystems and enterprise storage products. This role involves high-level architecture specification analysis, micro-architecture development, and high-performance RTL implementation using Verilog and SystemVerilog. Key responsibilities include managing asynchronous clock domain crossings, multiple power domains, low-power design, complex algorithms, deep computations, pipelining, and multi-threaded designs. The engineer must perform RTL optimization for timing closure, debug complex designs, and collaborate with verification, software, firmware, emulation, and validation teams. Technical requirements include experience with third-party IP integration and lab support for silicon validation. Preferred domain knowledge includes PCIe, CXL, and AMBA protocols, as well as RAID storage and PCIe switch designs. Candidates must possess a relevant engineering degree and five years of experience.

Skills

Verilog SystemVerilog RTL Design PCIe CXL AMBA Micro-architecture Timing Closure Low-power Design Emulation Validation RAID Storage

What you'll do

  • Analyze and author high-level architecture specifications.
  • Develop and document micro-architecture designs.
  • Implement high-performance Verilog/SystemVerilog RTL based on design specifications.
  • Optimize RTL to achieve timing closure.
  • Debug RTL designs and provide robust technical solutions.
  • Support cross-functional teams to resolve RTL design issues.
  • Provide lab support for silicon during the validation process.

What we're looking for

  • Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Science, Computer Engineering, or an equivalent Engineering degree.
  • 5+ years of relevant industry experience.
  • In-depth knowledge of implementation and supporting RTL designs using Verilog/SystemVerilog.
  • Experience with high-performance RTL implementation including clock domain crossings, power domains, low-power design, and pipelining.
  • Ability to perform high-level architecture specification analysis and micro-architecture development.
  • Skills in RTL optimization for timing closure and robust RTL debugging.
  • Ability to work in person at the Colorado Springs, Colorado campus.
  • Knowledge of PCIe, CXL, AMBA protocols, RAID Storage designs, or PCIe Switch designs (preferred).

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