Principal FPGA / RTL Design Engineer, Signal Processing

Motorola Solutions

Confirmed live today High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Los Angeles, CA
Salary: $195,000–$235,000 / yr
Employment: Full-time
Posted: 4 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $197k

This role $215k

$151k $246k

below market most similar roles pay here above market

This role pays more than 61% of similar roles. Most pay $168,500–$224,875 — the blue band above. At the midpoint, this role pays about $215k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Motorola Solutions

Motorola Solutions, Inc. (NYSE: MSI) is a leading American technology company providing mission-critical communications, video security, and analytics for public safety and enterprise customers.

Motorola Solutions currently has 159 open roles on FindRole.

Listed pay typically runs $100,000–$130,000 across 121 roles with salary data.

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At a glance

TL;DR · Principal FPGA / RTL Design Engineer, Signal Processing

Role Posting Log in to save

The Principal FPGA / RTL Design Engineer – Signal Processing joins the FPGA Engineering team to support the research and development of advanced wireless systems. This role involves the entire development lifecycle from concept to field deployment, specifically focusing on the efficient implementation of novel signal processing algorithms for MIMO wireless networking products. Key responsibilities include digital design architecting, fixed point design of signal processing blocks, RTL coding, simulation, test bench development, FPGA synthesis, and timing closure. The candidate must utilize Xilinx FPGAs, SoCs, and the Vivado IDE while demonstrating expertise in multiple clock-domain, high-utilization designs. Required skills include fixed point binary arithmetic, digital signal processing, and hardware verification using logic analyzers. The work addresses challenging real-world communication needs for mission-critical MANET and MIMO communications systems.

Skills

FPGA RTL Design Digital Signal Processing Vivado Xilinx Python Perl MATLAB Hardware Verification Logic Analyzers ASIC Wireless Communication Simulation Timing Closure

What you'll do

Architect digital designs for wireless communication projects.
Design fixed-point signal processing blocks in coordination with systems engineers.
Perform RTL coding, simulation, and test bench development.
Execute FPGA synthesis and achieve timing closure.
Conduct hardware verification and troubleshooting using logic analyzers.
Provide technical support to the RF and Software Engineering teams.
Implement novel signal processing algorithms for MIMO wireless networking products.

What we're looking for

Bachelor of Science degree in Electrical Engineering, Computer Science, or related field.
Minimum 10 years of RTL design and FPGA implementation experience; OR 8 years with a Master of Science; OR 6 years with a PhD.
Demonstrated experience with fixed point binary arithmetic and digital signal processing designs.
Proven expertise working with multiple clock-domain, high-utilization FPGA designs.
Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.
Must be a U.S. Person (U.S. Citizen or U.S. Permanent Resident).
Basic MATLAB skills (preferred).
PhD degree.

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