Staff SoC Power Performance Verification Engineer

Arm Holdings

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Austin, TX
Salary
$198,100–$268,000 / yr
Posted
31 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $192k
This role $233k
$129k most similar roles pay here $283k

This role pays more than 85% of similar roles. Most pay $168,500–$216,250 — the shaded band above. At the midpoint, this role pays about $233k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 39 open roles on FindRole.

Listed pay typically runs $208,450–$282,050 across 38 roles with salary data.

Most-posted roles

View all roles at Arm Holdings

At a glance

TL;DR · Staff SoC Power Performance Verification Engineer

Staff SoC Power Performance Verification Engineer joins the System-on-Chip Performance Analysis Team to build early performance analysis platforms for future Arm System/SoC architecture. This role involves performing RTL performance analysis and verification for SoCs while providing technical leadership in collaboration with architecture, design, and modeling teams. Key responsibilities include implementing performance verification plans using simulation and emulation environments, conducting theoretical memory system optimizations, and developing debug infrastructure and visualization tools. The candidate will utilize Verilog, SystemVerilog, C, C++, and scripting languages like Python or Ruby to identify design bottlenecks and propose data-driven solutions. Essential expertise includes multiprocessor coherency, memory ordering, I/O ordering, interrupts, MMU, and cache architectures. The role focuses on solving complex system-level performance issues across CPU, GPU, and I/O workloads through workload characterization and analysis to influence future SoC and IP designs.

What you'll do

  • Perform RTL performance analysis and verification for System-on-Chip (SoC) designs.
  • Implement performance verification plans and debug using simulation and emulation environments.
  • Drive emulation-based studies including emulator bring-up and execution of complex system-level benchmarks.
  • Conduct theoretical analysis of memory system optimizations and analyze corresponding benchmark data.
  • Debug performance failures to identify design bottlenecks and propose architectural or RTL solutions.
  • Develop and enhance debug infrastructure, tooling, and visualization solutions for root-cause identification.
  • Leverage AI-based tools and automation to improve engineering productivity and analysis workflows.

What we're looking for

  • Proven experience in SoC RTL performance analysis and debug using hardware emulation platforms.
  • Hands-on experience with emulator bring-up, configuration, and development of new performance test cases.
  • Strong system-level performance debug experience across complex IP interactions including CPU, GPU, and I/O workloads.
  • Deep understanding of memory system architecture and interconnect design.
  • Excellent knowledge of Verilog and SystemVerilog.
  • Working knowledge of C, C++, and a scripting language such as Python or Ruby.
  • Proven understanding of multiprocessor coherency, memory ordering, I/O ordering, interrupts, MMU, and cache architectures.
  • Proficiency in Unix/Linux, source control systems, CPU instruction sets, ARM architecture, compilers, assemblers, or device drivers (preferred).

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