RTL IC Design Engineer

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Colorado Springs, COSan Jose, CA
Employment
Full-time
Posted
3 days ago
Freshness
Confirmed live yesterday
Closes
Apr 5, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $200k
$139k $271k
below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $170,869–$229,650.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 235 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 160 roles with salary data.

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At a glance

TL;DR · RTL IC Design Engineer

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The RTL IC Design Engineer joins the Data Center Solutions Group to develop next generation AI/ML ecosystems and enterprise storage products. This role involves high-level architecture specification analysis, micro-architecture development, and high-performance RTL implementation using Verilog and SystemVerilog. Key responsibilities include managing asynchronous clock domain crossings, multiple power domains, low-power design, complex algorithms, deep computations, pipelining, and multi-threaded designs. The engineer must converge designs to timing closure through RTL optimization and provide robust debugging solutions. Collaboration with cross-functional teams including Verification, Software, Firmware, Emulation, and Validation Engineering is required, alongside providing lab support for silicon validation. Technical competencies include knowledge of PCIe, CXL, AMBA protocols, RAID storage designs, and PCIe Switch designs to solve complex hardware problems within data center environments.

Skills

Verilog SystemVerilog RTL Design PCIe CXL AMBA Micro-architecture Timing Closure Low-power Design Emulation Validation RAID Storage Design Clock Domain Crossing

What you'll do

  • Analyze and author high-level architecture specifications.
  • Develop and document micro-architecture designs.
  • Implement high-performance Verilog/SystemVerilog RTL based on design specifications.
  • Optimize RTL to achieve timing closure.
  • Debug RTL designs and provide robust technical solutions.
  • Support cross-functional teams to resolve RTL design issues.
  • Provide lab support for silicon during the validation process.

What we're looking for

  • Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Science, Computer Engineering, or an equivalent Engineering degree.
  • 5+ years of relevant industry experience.
  • In-depth knowledge of implementation and supporting RTL designs using Verilog/SystemVerilog.
  • Ability to perform high-level architecture specification analysis, micro-architecture development, and documentation.
  • Experience in high-performance RTL implementation including clock domain crossings, power domains, low-power design, and pipelining.
  • Ability to converge designs to timing closure using RTL optimization strategies and robust debugging skills.
  • Experience with PCIe, CXL, AMBA protocols, RAID storage designs, or PCIe switch designs (preferred).
  • Ability to work in person as remote work is not allowed.

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