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Active Keyword: RTL Design Remove filter Clear all

16 of up to 20 (filtered)

ASIC/RTL Design Engineer for High-speed Interfaces

Qualcomm

San Diego, CA 3 days ago $140,000–$210,000
Actively hiring Confirmed live yesterday Posted this week High trust Below market
RTL ASIC Design SerDes DDR PCIe USB UFS MIPI VCS Fusion Compiler PrimeTime Power Compiler Spyglass Python Perl DFT STA CDC GDSII
4+ yrs exp
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CPU Micro-architect/RTL Designer

Qualcomm

Austin, TX +1 12 days ago $148,300–$250,700
Actively hiring Confirmed live yesterday Trusted Competitive pay
RTL Verilog VHDL Python Perl Microarchitecture Logic Design Functional Verification Waveform Debugging Instruction Fetch Branch Prediction
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RTL Design & Integration Engineer

Amd

San Jose, CA 20 days ago $166,400–$249,600
Actively hiring Confirmed live 2 days ago High trust Above market
Verilog SystemVerilog RTL Design VLSI FPGA Python Tcl Perl Shell Synopsys Design Compiler Primetime VCS Cadence Virtuoso UVM OVM STA Synthesis P&R GDSII Simulation
Hybrid
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CPU Micro-architect/RTL Designer

Qualcomm

Austin, TX +1 38 days ago $211,900–$317,900
Actively hiring Confirmed live yesterday Trusted Above market
RTL Design Microarchitecture Verilog VHDL Python Perl Logic Design Waveform Debugging Simulators Instruction Fetch and Decode Branch Prediction Out-of-Order Execution
8+ yrs exp
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CPU Micro-Architecture and RTL Design Engineer (RISC-V)

Qualcomm

Santa Clara, CA +1 43 days ago $167,100–$250,700
Actively hiring Confirmed live 2 days ago Low trust Competitive pay
RISC-V RTL Design Verilog VHDL Microarchitecture Python Perl Logic Design Functional Verification Waveform Debugging Instruction Fetch and Decode Branch Prediction Out-of-Order Execution
4+ yrs exp
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Senior Engineer, GPU RTL Design

Samsung Electronics

Remote (Austin, TX) 43 days ago $124,000–$208,400
Actively hiring Confirmed live yesterday Trusted Below market
RTL Verilog SystemVerilog GPU SoC ASIC Synthesis Linting Timing Analysis PPA Microarchitecture Datapath Cache Design Memory Systems
4+ yrs exp Remote
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CPU Core RTL Design Engineer

Amd

Austin, TX 64 days ago $178,400–$267,600
Actively hiring Confirmed live 2 days ago High trust Above market
Verilog SystemVerilog RTL Design CPU Architecture ASIC SoC Logic Design Synthesis Timing Closure Python Tcl DFT Power Management Post-silicon Debug Place-and-Route
Hybrid
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Processor Micro Architect RTL Design Engineer

Qualcomm

San Diego, CA 87 days ago $180,400–$270,600
Actively hiring Confirmed live 2 days ago Trusted Above market
RTL Verilog System Verilog ASIC Design Logic Design Digital Design Static Timing Analysis Low Power Design Microprocessor Architecture Cache Bus Protocol Linting Clock Domain Crossing GDS2 Synthesis Simulation Regression
6+ yrs exp
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Senior FPGA / RTL Design Engineer, Signal Processing

Motorola Solutions

Los Angeles, CA +1 95 days ago $125,000–$195,000
Actively hiring Confirmed live yesterday Trusted Below market
FPGA Digital Signal Processing RTL Xilinx Vivado MATLAB Logic Analyzers Hardware Verification Timing Closure Synthesis Simulation Test Bench Development MIMO
6+ yrs exp Hybrid
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Principal FPGA / RTL Design Engineer, Signal Processing

Motorola Solutions

Los Angeles, CA +1 102 days ago $175,000–$225,000
Actively hiring Confirmed live 2 days ago High trust Competitive pay
FPGA RTL Design Xilinx Vivado Digital Signal Processing Python Perl MATLAB Logic Analyzers Timing Closure Simulation test bench development Wireless Communication Systems
10+ yrs exp Hybrid
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Senior RTL Design Engineer

SpaceX

Irvine, CA 113 days ago $165,000–$260,000
Actively hiring Confirmed live 2 days ago Low trust Competitive pay
Verilog System Verilog ASIC SoC RTL Design Python AXI AHB Synthesis Timing Closure HDL Simulators EDA Tools Clock Domain Crossing Power Optimization Silicon Bring-up
5+ yrs exp
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Senior RTL Design Engineer, Silicon Engineering

SpaceX

Palo Alto, CA 113 days ago $175,000–$280,000
Actively hiring Confirmed live yesterday Low trust Above market
Verilog System Verilog ASIC SoC RTL Design Python AXI AHB HDL Simulators EDA Tools Timing Closure Synthesis Clock Domain Crossing Power Optimization Silicon Bring-up
5+ yrs exp
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Senior RTL Design Engineer

SpaceX

Redmond, WA 113 days ago $165,000–$260,000
Actively hiring Confirmed live yesterday Low trust Competitive pay
Verilog System Verilog ASIC SoC RTL Design Python AXI AHB Synthesis Timing Closure HDL Simulators HDL Lint Tools Clock Domain Crossing Power Optimization
5+ yrs exp
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Processor ASIC RTL Design Engineer

Qualcomm

San Diego, CA 126 days ago $127,200–$190,800
Actively hiring Confirmed live 2 days ago Trusted Below market
RTL system Verilog Verilog ASIC Design Logic Design Digital Design Static Timing Analysis Clock Domain Crossing Microprocessor Design Bus Interface Cache Linting LEC CLP GDS2 Synthesis
2+ yrs exp
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Integration RTL Design Engineer

Amd

San Jose, CA 169 days ago $166,400–$249,600
Actively hiring Confirmed live yesterday High trust Competitive pay
Verilog RTL Design ASIC SoC STA SDC PrimeTime Tempus AMBA AXI AHB APB PCIe CXL Python Perl Tcl DFT Low-Power Design
Hybrid
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RTL Design Engineer, Silicon Engineering

SpaceX

Irvine, CA 178 days ago $125,000–$145,000
Actively hiring Confirmed live yesterday Low trust Below market
RTL Design SystemVerilog Verilog VHDL ASIC FPGA Python DSP AXI AHB APB EDA Tools HDL Simulators
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