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Active Keyword: RTL Design Remove filter Clear all

20 of up to 20 (filtered)

CPU Core RTL Design Engineer

Amd

Austin, TX 5 days ago $144,800–$217,200
Actively hiring Confirmed live today Posted this week High trust Competitive pay
Verilog SystemVerilog RTL Design CPU Architecture ASIC Logic Design Synthesis Timing Closure Place-and-Route Python Tcl DFT Post-Silicon Debug Power Management Cache Hierarchy TLB Branch Prediction
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RTL IC Design Engineer

Broadcom

Colorado Springs, CO +1 6 days ago $101,000–$162,000
Actively hiring Confirmed live today Posted this week High trust Below market
Verilog SystemVerilog RTL Design PCIe CXL AMBA Micro-architecture Timing Closure Low-power Design Emulation Validation RAID Storage
5+ yrs exp
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Wireless RTL Design Engineer

Apple Inc

Sunnyvale, CA 10 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
RTL Design MATLAB DSP Fixed-point Synthesis CDC Power Analysis Microarchitecture VLSI SoC Signal Processing Bit-true Verification
10+ yrs exp
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Wireless RTL Design Engineer

Apple Inc

San Diego, CA 10 days ago $175,000–$308,500
Actively hiring Confirmed live today Trusted Above market
RTL Design MATLAB DSP Fixed-point Synthesis CDC Power Analysis VLSI SoC Microarchitecture Signal Processing
10+ yrs exp
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Wireless RTL Design Engineer

Apple Inc

Irvine, CA 10 days ago $175,000–$308,500
Actively hiring Confirmed live today Trusted Above market
RTL Design MATLAB DSP Fixed-point Synthesis CDC Power Analysis VLSI SoC Microarchitecture front end CAD tools
10+ yrs exp
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RTL Methodology Silicon Design Engineer

Amd

Austin, TX 11 days ago $178,400–$267,600
Actively hiring Confirmed live today High trust Above market
RTL Design SystemVerilog Verilog Python Go Java C# TypeScript Perl Ruby Shell TCL LLM RAG Agentic Frameworks Static Analysis Linting Verible Slang Verilator Surelog Synthesis Physical Design Place and Route Timing Closure
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Wireless RTL Design Engineer

Apple Inc

Sunnyvale, CA 12 days ago $129,300–$225,300
Actively hiring Confirmed live today Trusted Competitive pay
RTL Design MATLAB DSP Fixed-point Synthesis CDC Power Analysis VLSI SoC Microarchitecture Design Verification front end CAD tools
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Wireless RTL Design Engineer

Apple Inc

San Diego, CA 12 days ago $122,700–$214,300
Actively hiring Confirmed live today Trusted Below market
RTL Design MATLAB DSP Fixed-point Synthesis CDC Power Analysis VLSI SoC Microarchitecture front end CAD
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Wireless RTL Design Engineer

Apple Inc

Irvine, CA 12 days ago $122,700–$214,300
Actively hiring Confirmed live today Trusted Below market
RTL Design MATLAB DSP Fixed-point Synthesis CDC Power Analysis VLSI SoC Microarchitecture front end CAD tools
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Senior Engineer, GPU RTL Design

Samsung Electronics

Austin, TX +1 18 days ago $124,000–$208,400
Actively hiring Confirmed live today Trusted Below market
Verilog SystemVerilog RTL Design ASIC Design GPU Architecture Microarchitecture Synthesis Linting Timing Analysis SoC Hardware Design PPA Digital Design Cache Design Memory Systems Datapath Control Logic
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Senior Engineer, GPU RTL Design - Pixel Pipe

Samsung Electronics

San Jose, CA 18 days ago $124,000–$208,400
Actively hiring Confirmed live today Trusted Below market
Verilog SystemVerilog RTL Design GPU Architecture SoC ASIC Design Flow Linting Synthesis Timing Analysis Microarchitecture PPA Digital Design Debug Simulation
2+ yrs exp
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RTL IC Design Engineer

Broadcom

Colorado Springs, CO +1 19 days ago
Actively hiring Confirmed live today Low trust
Verilog SystemVerilog RTL Design PCIe CXL AMBA Micro-architecture Timing Closure Low-power Design Emulation Validation RAID Storage Design Clock Domain Crossing
5+ yrs exp
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Principal FPGA / RTL Design Engineer, Signal Processing

Motorola Solutions

Los Angeles, CA 20 days ago $195,000–$235,000
Actively hiring Confirmed live today Trusted Competitive pay
FPGA RTL Design Digital Signal Processing Vivado Xilinx Python Perl MATLAB Hardware Verification Logic Analyzers ASIC Wireless Communication Simulation Timing Closure
10+ yrs exp Hybrid
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Senior FPGA / RTL Design Engineer, Signal Processing

Motorola Solutions

Los Angeles, CA 20 days ago $155,000–$195,000
Actively hiring Confirmed live yesterday Trusted Below market
FPGA RTL Digital Signal Processing Vivado Xilinx MATLAB Hardware Verification Logic Analyzers ASIC Simulation Test Bench Development Timing Closure MIMO MANET
6+ yrs exp Hybrid
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CPU RTL Design Engineer

Amd

Austin, TX 20 days ago $121,680–$182,520
Actively hiring Confirmed live today High trust Below market
Verilog SystemVerilog RTL Design CPU Architecture ASIC SoC Logic Design Synthesis Static Timing Analysis Place-and-Route Python Tcl DFT Post-Silicon Debug Power Management Timing Closure
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Interconnect Micro-architect/RTL Design Engineer

Amd

Austin, TX 25 days ago $178,400–$267,600
Actively hiring Confirmed live today High trust Above market
Verilog System Verilog RTL Design C C++ Python Perl x86 ARM Digital Design DFT MMU High-Speed Design
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CPU Micro-Architecture and RTL Design Engineer (RISC-V)

Qualcomm

Santa Clara, CA +1 25 days ago $175,600–$263,400
Actively hiring Confirmed live today Trusted Competitive pay
RISC-V RTL Design Verilog VHDL Microarchitecture Python Perl Logic Design Functional Verification Waveform Debugging Simulators Out-of-Order Execution
4+ yrs exp
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Processor ASIC RTL Design Engineer

Qualcomm

San Diego, CA 29 days ago $101,400–$152,200
Actively hiring Confirmed live today Trusted Below market
ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Design Verification Scripting
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Director, CPU RTL Design Engineering

Amd

Remote (Santa Clara, CA) 31 days ago $248,800–$373,200
Actively hiring Confirmed live today High trust Above market
RTL Design x86 Computer Architecture Processor Pipeline Memory Hierarchy Instruction Set Architecture Logic Design Python Ruby Perl Silicon Development Lifecycle Tapeout Scripting Automation
Remote
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Senior RTL Design Engineer

Amd

San Jose, CA 32 days ago $200,000–$300,000
Actively hiring Confirmed live today High trust Above market
Verilog SystemVerilog UVM DFT RTL Design Python Tcl Perl Shell Static Timing Analysis ASIC SoC FPGA Synopsys Cadence PCIe SerDes HBM Design Automation
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