Senior RTL Design Engineer

Amd

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CA
Salary
$200,000–$300,000 / yr
Posted
6 days ago
Freshness
Confirmed live today
Closes
Sep 24, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $196k
This role $250k
$133k most similar roles pay here $318k

This role pays more than 88% of similar roles. Most pay $168,200–$223,575 — the shaded band above. At the midpoint, this role pays about $250k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 374 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 374 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Senior RTL Design Engineer

Role Posting Log in to save

As a Sr. RTL Design Engineer on the FPGA Product and Platform development team, you will contribute to the technical execution of Adaptive & Embedded Computing Group device programs from definition through productization. You will design and implement RTL for complex digital and mixed-signal blocks using Verilog and SystemVerilog while supporting physical design activities like synthesis, DFT implementation, and Static Timing Analysis. Your daily work involves collaborating with functional verification teams using UVM and developing automation tools via Perl, Tcl, Shell, and Python. The role focuses on the development of silicon implementations for high-speed interfaces including HBM, SerDes, PCIe, and memory subsystems. You will navigate the full ASIC/SoC development flow to solve complex engineering challenges within the domain of FPGA architectures and advanced hardware integration for integrated circuit design.

Skills

Verilog SystemVerilog UVM Python Tcl Perl Shell DFT STA ASIC SoC FPGA Synopsys Cadence VCS PrimeTime GDS HBM PCIe SerDes

What you'll do

  • Design and implement RTL for complex digital and mixed-signal blocks using Verilog and SystemVerilog.
  • Participate in all stages of the design flow from initial RTL development through GDS implementation.
  • Support physical design activities including synthesis, DFT implementation, place-and-route, and Static Timing Analysis (STA).
  • Collaborate with Functional Verification teams to support block-level verification using constrained-random and directed test environments.
  • Develop and maintain design automation flows and tools using Perl, Tcl, Shell, and Python.
  • Implement DFT solutions for large-scale SoCs including scan, compression, MBIST, and LBIST technologies.
  • Resolve technical issues and ensure project milestones are met across global engineering teams.

What we're looking for

  • Bachelor's or master’s degree in electrical engineering, computer engineering, or a related field.
  • Experience designing and implementing RTL for complex digital and mixed-signal blocks using Verilog and SystemVerilog.
  • Proficiency in scripting languages including Perl, Tcl, Shell, and Python to maintain design automation flows.
  • Knowledge of physical design activities such as synthesis, DFT implementation, place-and-route, and Static Timing Analysis (STA).
  • Experience with UVM/OVM verification methodologies, testbench development, and simulation environments (preferred).
  • Experience with high-speed interfaces and complex IPs like HBM, Die-to-Die, SerDes, PCIe, and memory subsystems (preferred).
  • Hands-on experience with industry-standard EDA tools such as Synopsys and Cadence suites (preferred).
  • Proven experience implementing DFT solutions for large-scale SoCs including scan, compression, MBIST, and LBIST (preferred).

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