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20 of up to 20 (filtered)

Director, Cache RTL

Amd

Fort Collins, CO 3 days ago $216,080–$324,120
Actively hiring Confirmed live today Posted this week High trust Above market
RTL Design Microarchitecture Verilog SystemVerilog HDL Cache Architecture CPU Coherency SoC Chiplet Lint CDC RDC Scripting Low-Power Design RAS ECC Tapeout Physical Design Design For Test
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CPU Core RTL Design Engineer

Amd

Austin, TX 6 days ago $144,800–$217,200
Actively hiring Confirmed live today Posted this week High trust Competitive pay
Verilog SystemVerilog RTL Design CPU Architecture ASIC Logic Design Synthesis Timing Closure Place-and-Route Python Tcl DFT Post-Silicon Debug Power Management Cache Hierarchy TLB Branch Prediction
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Core RTL/Microarchitecture Power Lead

Amd

Santa Clara, CA 6 days ago $232,000–$348,000
Actively hiring Confirmed live today Posted this week High trust Above market
Microprocessor Architecture RTL Verilog System Verilog Low Power Design Logic Design PTPX Python Ruby Perl Shell Synthesis Place and Route Timing Closure Physical Design AI LLMs Performance Simulators
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RTL IC Design Engineer

Broadcom

Colorado Springs, CO +1 6 days ago $101,000–$162,000
Actively hiring Confirmed live today Posted this week High trust Below market
Verilog SystemVerilog RTL Design PCIe CXL AMBA Micro-architecture Timing Closure Low-power Design Emulation Validation RAID Storage
5+ yrs exp
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Senior ASIC RTL Engineer

Cisco

San Jose, CA +1 6 days ago $167,700–$245,200
Actively hiring Confirmed live today Posted this week High trust Competitive pay
Verilog System Verilog DFT MBIST AMBA AXI APB AHB JTAG UPF Formal Verification Linting CDC Checkers Synthesis Post-Silicon Debug Power Optimization Power Estimation
7+ yrs exp Hybrid
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ASIC Technical Leader, RTL

Cisco

San Jose, CA +1 6 days ago $186,900–$267,700
Actively hiring Confirmed live today Posted this week High trust Above market
Verilog System Verilog DFT MBIST AMBA AXI APB AHB JTAG UPF Formal Verification Linting CDC Checkers Synthesis Post-Silicon Debug RTL
10+ yrs exp Hybrid
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Wireless RTL Design Engineer

Apple Inc

Sunnyvale, CA 10 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
RTL Design MATLAB DSP Fixed-point Synthesis CDC Power Analysis Microarchitecture VLSI SoC Signal Processing Bit-true Verification
10+ yrs exp
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Wireless RTL Design Engineer

Apple Inc

San Diego, CA 10 days ago $175,000–$308,500
Actively hiring Confirmed live today Trusted Above market
RTL Design MATLAB DSP Fixed-point Synthesis CDC Power Analysis VLSI SoC Microarchitecture Signal Processing
10+ yrs exp
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Wireless RTL Design Engineer

Apple Inc

Irvine, CA 10 days ago $175,000–$308,500
Actively hiring Confirmed live today Trusted Above market
RTL Design MATLAB DSP Fixed-point Synthesis CDC Power Analysis VLSI SoC Microarchitecture front end CAD tools
10+ yrs exp
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RTL Methodology Silicon Design Engineer

Amd

Austin, TX 11 days ago $178,400–$267,600
Actively hiring Confirmed live today High trust Above market
RTL Design SystemVerilog Verilog Python Go Java C# TypeScript Perl Ruby Shell TCL LLM RAG Agentic Frameworks Static Analysis Linting Verible Slang Verilator Surelog Synthesis Physical Design Place and Route Timing Closure
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Wireless RTL Design Engineer

Apple Inc

Sunnyvale, CA 12 days ago $129,300–$225,300
Actively hiring Confirmed live today Trusted Competitive pay
RTL Design MATLAB DSP Fixed-point Synthesis CDC Power Analysis VLSI SoC Microarchitecture Design Verification front end CAD tools
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Wireless RTL Design Engineer

Apple Inc

San Diego, CA 12 days ago $122,700–$214,300
Actively hiring Confirmed live today Trusted Below market
RTL Design MATLAB DSP Fixed-point Synthesis CDC Power Analysis VLSI SoC Microarchitecture front end CAD
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Wireless RTL Design Engineer

Apple Inc

Irvine, CA 12 days ago $122,700–$214,300
Actively hiring Confirmed live today Trusted Below market
RTL Design MATLAB DSP Fixed-point Synthesis CDC Power Analysis VLSI SoC Microarchitecture front end CAD tools
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Senior Engineer, GPU RTL Design

Samsung Electronics

Austin, TX +1 18 days ago $124,000–$208,400
Actively hiring Confirmed live today Trusted Below market
Verilog SystemVerilog RTL Design ASIC Design GPU Architecture Microarchitecture Synthesis Linting Timing Analysis SoC Hardware Design PPA Digital Design Cache Design Memory Systems Datapath Control Logic
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Senior Staff Engineer, GPU RTL Firmware

Samsung Electronics

Austin, TX 18 days ago $180,200–$297,200
Actively hiring Confirmed live today Trusted Above market
Firmware Development C C++ Assembly RISC-V Verilog SystemVerilog RTL Design ASIC Flow Vulkan OpenGL Direct3D OpenCL GPU Architecture SoC Architecture Bring-up Debug
10+ yrs exp
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Staff Engineer, GPU RTL Power Management

Samsung Electronics

Austin, TX 18 days ago $151,000–$251,800
Actively hiring Confirmed live today Trusted Competitive pay
Verilog SystemVerilog RTL Design GPU Architecture SoC Power Management Python Perl Microarchitecture Clock Domain Crossing Hardware Design Firmware Digital Design
5+ yrs exp
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Senior Engineer, GPU RTL Design - Pixel Pipe

Samsung Electronics

San Jose, CA 18 days ago $124,000–$208,400
Actively hiring Confirmed live today Trusted Below market
Verilog SystemVerilog RTL Design GPU Architecture SoC ASIC Design Flow Linting Synthesis Timing Analysis Microarchitecture PPA Digital Design Debug Simulation
2+ yrs exp
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RTL IC Design Engineer

Broadcom

Colorado Springs, CO +1 19 days ago
Actively hiring Confirmed live today Low trust
Verilog SystemVerilog RTL Design PCIe CXL AMBA Micro-architecture Timing Closure Low-power Design Emulation Validation RAID Storage Design Clock Domain Crossing
5+ yrs exp
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SoC RTL Performance Analysis Engineer

Arm Holdings

Austin, TX 20 days ago $198,100–$268,000
Actively hiring Confirmed live today High trust Above market
SoC RTL Performance Analysis Hardware Emulation Verilog SystemVerilog C C++ Python Ruby Unix Linux Git Subversion ARM Architecture Memory System Architecture Cache Architecture MMU CPU GPU I/O Compilers Assemblers Device Drivers
Hybrid
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Principal FPGA / RTL Design Engineer, Signal Processing

Motorola Solutions

Los Angeles, CA 20 days ago $195,000–$235,000
Actively hiring Confirmed live today Trusted Competitive pay
FPGA RTL Design Digital Signal Processing Vivado Xilinx Python Perl MATLAB Hardware Verification Logic Analyzers ASIC Wireless Communication Simulation Timing Closure
10+ yrs exp Hybrid
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