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17 of up to 20 (filtered)

Principal FPGA / RTL Design Engineer - Signal Processing

Motorola Solutions

Los Angeles, CA 3 days ago $175,000–$225,000
Actively hiring Posted this week Verified listing Competitive pay
Vivado Xilinx FPGA RTL Python Perl MATLAB Fixed_point_design Multiple_clock_domain_FPGA_designs Digital_signal_processing Wireless_communication_systems
Hybrid
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CPU RTL/AI Micro-Architect - AI Development

Qualcomm

Austin, TX 3 days ago $179,000–$268,400
Actively hiring Posted this week Verified listing Above market
AI Python Verilog SystemVerilog VHDL Kubernetes Docker CI/CD Prometheus Grafana AWS Git Jenkins PostgreSQL SQLite
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Senior Engineer, GPU RTL Power

Samsung Electronics

Remote (3900 N Capital Of Texas Hwy, Austin, Tx, Usa, US) 7 days ago $124,000–$186,000
Actively hiring Posted this week Verified listing Below market
SystemVerilog PowerArtist PTPX Empower Python Perl ASIC RTL Synthesis Timing Analysis Clock Gating Power Gating Physical Design STA High-Performance Digital Design GPU Architecture CPU Architecture Scripting Languages Data-Driven Debugging
Remote
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Staff System Software Engineer, RTL-to-GDS Flow Platform

Nvidia

Santa Clara, CA 13 days ago $184,000–$287,500
Actively hiring Verified listing Above market
Tcl Python Perl Make YAML Linux Go C++ LSF Slurm NFS Docker CI/CD Prometheus Grafana Git SVN Jenkins Kubernetes AWS Azure Google Cloud PostgreSQL MongoDB
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CPU Systems RTL Engineer

Qualcomm

Santa Clara, CA 14 days ago $167,100–$250,700
Actively hiring Verified listing Above market
C C++ Python Perl Verilog VHDL UVM SystemC Cadence Synopsys ModelSim Questa TCL SV CI/CD
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Senior Engineer, GPU RTL Design - Pixel Pipe

Samsung Electronics

Remote (3655 N 1St St, San Jose, Ca, Usa, US) 16 days ago $139,000–$208,400
Actively hiring Below market
Verilog SystemVerilog RTL design GPU architecture ASIC design flows linting synthesis timing analysis design quality checks microarchitecture development control logic datapath design memory systems fixed-function acceleration pixel processing pipelines performance optimization power optimization firmware enablement
Remote
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RISCV CPU System RTL Engineer

Qualcomm

Santa Clara, CA 21 days ago $142,200–$213,400
Actively hiring Competitive pay
Verilog VHDL Perl Python Power management Debugging tools RTL design RISCV CPU architecture High-performance systems Low-power microarchitecture Telemetry architecture Interrupt controller Timer synchronization RAS and safety mechanisms Architecture and performance monitoring Scripting languages Simulation tools Waveform debugging tools
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Processor ASIC RTL Design Engineer

Qualcomm

San Diego, CA 27 days ago $127,200–$190,800
Actively hiring Below market
SystemVerilog RTL Verilog Linting CDC LEC CLP Processor integration Bus interface Cache Digital design Logic design
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Processor Micro Architect RTL Design Engineer (Multiple Levels)

Qualcomm

San Diego, CA 27 days ago $180,400–$270,600
Actively hiring Above market
Verilog System Verilog RTL digital design logic design cache memory coherency bus interface multi-core microprocessor architecture low power design functional verification static timing analysis formal verification PLDRC clock domain crossing
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CPU Micro-Architecture and RTL Design Engineer (RISC-V)

Qualcomm

Santa Clara, CA 27 days ago $167,100–$250,700
Actively hiring Competitive pay
Verilog VHDL Perl Python RTL Microarchitecture Instruction_fetch_and_decode Branch_prediction Out_of_order_execution Integer_and_floating_point_execution Load_store_execution Prefetching Cache_and_memory_subsystems Logic_design_principles Timing_and_power_implications Low_power_microarchitecture_techniques
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CPU Micro-Architect RTL Engineer

Qualcomm

Austin, TX 27 days ago $154,000–$231,000
Actively hiring Competitive pay
RISC-V RTL Verilog SystemC VHDL Processor pipelines Out-of-order execution Load/store units Caches Cache coherence Memory hierarchy Multi-processor systems Multi-threaded systems Low-power design Performance optimization Area and timing goals Communication skills Collaboration skills Teamwork skills
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Principal RTL Design Engineer - QGOV

Qualcomm

San Diego, CA 49 days ago $192,000–$288,000
Actively hiring Above market
Verilog SystemVerilog RTL FPGA ASIC Python Perl PCIe UART I2C DDRx SPI USB ARM RISC-V Multi-Power-Domain Multi-Clock-Domain Scripting Automation Design-for-Testability Emulation Synthesis
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CPU RTL Methodology Engineer

Qualcomm

Santa Clara, CA 59 days ago $198,700–$298,100
Actively hiring Above market
Python Git Verilog SystemVerilog TCL Perl Bash CI/CD CAD RTL
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CPU Micro-architect/RTL Designer (Multiple Locations)

Qualcomm

Austin, TX 79 days ago $148,300–$250,700
Actively hiring Competitive pay
Verilog VHDL Perl Python Waveform debugging tools Simulators Instruction fetch and decode Branch prediction Instruction scheduling Register renaming Out-of-order execution Integer execution Floating point execution Load/store execution Prefetching Cache subsystems Memory subsystems Logic design principles Timing analysis Power analysis Low power techniques High performance techniques
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Staff/Sr. Staff RTL Design Engineer - QGOV

Qualcomm

San Diego, CA 94 days ago $164,000–$246,000
Actively hiring Competitive pay
Verilog SystemVerilog RTL FPGA ASIC Python Perl PCIe UART I2C DDRx SPI USB ARM RISC-V Multi-Power-Domain Multi-Clock-Domain Scripting Automation Digital-Design-Tools
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