below marketmost similar roles pay hereabove market
This role pays more than
73%
of similar roles. Most pay
$208,725–$273,196
— the blue band above.
At the midpoint, this role pays about
$270k
versus about
$241k
for comparable roles.
Based on 240 similar postings.
Employer
About Amd
AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors
Amd currently has
496 open roles
on FindRole.
Listed pay typically runs
$172,000–$258,000
across 496 roles with salary data.
The Director, Cache RTL joins the Cores Organization to lead the Cache Hierarchy RTL organization, specifically overseeing L2 and L3 cache designs for next-generation CPU cores. This role serves as both a senior technical leader and people leader, managing first-line managers and senior technical leads to own microarchitecture, RTL implementation, and design quality from feature definition through tapeout. The successful candidate will translate architecture into optimized microarchitecture, managing trade-offs for cache controllers, arrays, coherency, and routing fabric across multiple concurrent programs. Key technical requirements include expertise in Verilog/SystemVerilog HDL, Digital RTL Design, lint, CDC/RDC, formal, and scripting. The role addresses the business problem of delivering high-performance, energy-efficient cache designs for server, client, and gaming products while ensuring reliable, testable, and manufacturable RTL for SOC and chiplet integration.
Lead the functional L2 and L3 cache RTL teams and own microarchitecture, RTL implementation, and design quality.
Translate architecture into optimized microarchitecture by driving feature definition and performance, power, and area trade-offs.
Manage RTL execution across multiple concurrent programs, including milestone commitments, staffing, and schedule risk mitigation.
Partner with Physical Design and Design Verification leadership to ensure RTL is optimized for timing, area, and testability.
Resolve complex interactions between core, cache, and SOC/chiplet designs while driving IP reuse across product lines.
Champion innovation in design methodology, automation, and AI-assisted engineering to improve team productivity.
Recruit, develop, and mentor managers and technical leaders to build a high-accountability team culture.
Represent the Cache Hierarchy organization in cross-functional reviews and create technical presentations for senior executives.
What we're looking for
Bachelor’s, master’s, or doctoral degree in Electrical Engineering, Computer Science, Computer Engineering, or a similar field.
Extensive experience leading RTL and microarchitecture teams, including managing managers, through multiple tapeouts of high-performance CPU, cache, or SOC designs (preferred).
Deep expertise in Cache architecture development and execution, including Cache Controller and Array RTL implementation (preferred).
Prior experience with CPU Coherency, Coherent NOC, Cache Allocation and Replacement Policy, Prefetch interaction, Quality of Service, Fairness and Forward Progress architecture and implementation (preferred).
Prior experience with low-power design techniques and RAS features (ECC, error detection and handling) in cache and memory subsystems (preferred).
Prior experience executing multiple concurrent programs with shared or configurable IP, and delivering IP to SOC and chiplet integration teams (preferred).
Strong command of Digital RTL Design, Verilog/SystemVerilog HDL, design-quality flows (lint, CDC/RDC, formal), and Scripting (preferred).
Multiple years hardware design experience, including several years of people leadership (preferred).