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Verilog VHDL SystemVerilog SOC Architecture DRAM Interface Design Synthesis Formal Verification Timing Closure Signal Integrity Physical Implementation HDL +6 more Show less

Physical Design Place and Route Static Timing Analysis Physical Verification Formal Equivalency Verification IR-Drop Electromigration TCL Python Synopsys Fusion Compiler PrimeClosure Primetime Formality VCLP Star-RC Redhawk SC Cadence Innovus Siemens Calibre ASIC SOC +15 more Show less

Verilog SystemVerilog RTL Design SoC PCIe HBM AMBA AXI DMA Synthesis Timing Constraints CDC Lint RDC DFT Python Perl Agile Post-Silicon Debug +13 more Show less

ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Scripting SoC Circuit Design +5 more Show less

RTL Verilog System Verilog ASIC SoC Microarchitecture Synthesis Clock Domain Crossing Lint PPA Post-Silicon Debug Network on Chip Digital Design +8 more Show less

ASIC RTL SoC ARM DDR UCIe Ethernet AMBA DFT STA Synthesis Lint CDC PPA silicon bring up ATE Logic Design +12 more Show less

3D Memory ASIC Design RTL Verilog Verilog-A Verilog-AMS C C++ Python Perl Matlab EDA Tools HBM3/4 LPDDR PCIe UCIe UAL SRAM DRAM FLASH 2.5D/3D Integration +16 more Show less

Quantum Engineering Readout Circuitry Semiconductor Devices Cryogenic Microwave Experiments Low-Noise Amplifiers Simulation Artificial Intelligence Performance Modeling Hardware Development +4 more Show less

Python Claude Innovus ICC2 Calibre Tcl Docker OpenAI API Pinecone Weaviate RAG LLM MLPD STA DRC EDA Tools Vector Databases +12 more Show less

UVM SystemVerilog C++ Python Ruby Perl Verilog VHDL Agile Makefiles FPGA Emulation Assertion Functional Coverage Co-Pilot Scripting +11 more Show less

ASIC Physical Design Floorplanning Power Planning Clock Tree Synthesis Static Timing Analysis Signal Integrity RC Extraction DFT UPF Python Tcl Perl Shell Linux Unix Cadence Innovus Synopsys Fusion Compiler Synopsys PrimeTime +14 more Show less

Silicon Photonics SKILL DRC LVS Verilog-A Ansys Lumerical ZeMax MATLAB Python FDTD FDE EME DWDM Co-packaged Optics (CPO) +9 more Show less

C System Design Virtualization Software-Defined Networking Network Functions Virtualization Big Data Agile Capacity Planning Network Architecture Network Design Systems Engineering Technical Writing +7 more Show less

Electrical Engineering Data Center Design Power Generation Grounding Liquid Cooling Commissioning Technical Writing Contract Administration MSDS lockout/tag out High-Density Compute +6 more Show less

Electrical Engineering Data Center Design Power Generation Grounding Liquid Cooling Commissioning Technical Writing MSDS lockout/tag out Contract Administration High-Density Compute +6 more Show less

Analog Circuit Design High Voltage DC Power Systems SPICE Cadence Mentor Graphics Altium Prototyping Magnetics High Speed Design Spectrum Analyzers Oscilloscopes R&D +7 more Show less

SRAM Circuit Simulation Monte Carlo Analysis Static Timing Analysis Verilog BIST DFT NanoTime Ansys EMIR ESP-CV Liberate Schematic Capture Layout Design Functional Verification FinFET Nanosheet +11 more Show less

3D Memory ASIC Design RTL Verilog Verilog-A Verilog-AMS SoC Architecture HBM3/4 LPDDR PCIe UCIe Python C++ Matlab EDA Tools Mixed-Signal Design Performance Modeling +12 more Show less

ASIC SoC Physical Design RTL-to-GDSII Synthesis Place & Route STA Timing Closure Power Optimization TCL Python Synopsys Cadence PPA EM/IR Advanced Nodes +10 more Show less

FPGA RTL Design Xilinx Vivado Digital Signal Processing Python Perl MATLAB Logic Analyzers Timing Closure Simulation test bench development Wireless Communication Systems +8 more Show less