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UVM C Verilog SystemVerilog Python Docker CI/CD Kubernetes AWS Azure PostgreSQL Git Jenkins Prometheus Grafana +10 more Show less

UVM SystemVerilog Verilog PCIe NVMe RDMA Python CI/CD Kubernetes AWS GitHub JIRA PostgreSQL Mentor Graphics Questa Simulator Cadence Incisive Verilog Simulator +10 more Show less

Innovus Tempus Redhawk Voltus Calibre Python TCL Perl RTL2GDSII Hierarchical_Floorplanning Place_and_Route Static_Timing_Analysis Power_Integrity Equivalence_Checks Clock_Tree_Synthesis STA_setup Timing_Methodologies ECO_Implementation Functional_ECO Timing_ECO Automation Tapeouts 7nm 5nm 3nm +20 more Show less

HFSS CST FEKO Python MATLAB C++ Electromagnetics Antenna theory Radar systems Signal processing Control systems HPA Down-conversion architectures Near field measurement Far field anechoic chamber measurements Antenna Measurement Range Design +11 more Show less

Verilog VHDL SystemVerilog AMBA UART DRAM SERDES Cloud-based documentation tools CI/CD Python PostgreSQL +6 more Show less

Python Perl TCL AI CI/CD Docker Kubernetes AWS Azure PostgreSQL Git Jenkins Prometheus Grafana +9 more Show less

SystemVerilog Python Tcl Perl UVM Cadence_Genus Cadence_Conformal Cadence_Innovus Cadence_Voltus Cadence_Tempus Cadence_Modus DSP Low_Power_Design Lab_Automation Analog_IC_Design Digital_IC_Design Agentic_AI +12 more Show less

Verilog SystemVerilog Perl Tcl Python Reed-Solomon-Encoding CHI APB AMBA Synthesis STA CDC_checkers low_power_static_checkers linting_tools +9 more Show less

BMS EMPS SCADA PLC AI HPC Digital Twins MLOps Kubernetes Docker CI/CD AWS Azure Grafana Prometheus PostgreSQL Python Go Terraform Ansible GitLab JSON REST APIs +18 more Show less

TCL Python Synopsys Cadence RTL-to-GDSII ASIC SoC Physical Design Timing Closure Power Optimization EDA STA Signoff Place & Route Scripting Advanced Nodes PPA Trade-offs CPU Design Challenges Data-Driven Debugging +14 more Show less

Oracle Cloud Infrastructure AWS Kubernetes Docker CI/CD PostgreSQL Prometheus Grafana Bash Python Go Terraform Ansible JSON YAML RESTful APIs Linux Windows Server VMware Cisco RackScale Design Whiteline Design Greenfield Data Center Design AutoCAD Revit 3D Modeling Finite Element Analysis (FEA) +22 more Show less

ASIC RTL Verilog SystemC VHDL Python Perl Tcl CI/CD Git Linux ARM DDR UCIe AMBA DFT STA CDC Lint Synopsys Cadence Mentor Graphics ModelSim QuestaSIM +19 more Show less

Python ASIC verification FPGA verification

Python CI/CD

Python ASIC verification FPGA verification

Python CI/CD

AXI AHB RTL FPGA ASIC

AXI AHB RTL FPGA ASIC

AXI AHB RTL FPGA ASIC

SRAM Register_File High_Performance_Design Low_Power_Design Semiconductor_Device_Fundamentals Variation_Aware_Simulation Custom_Memory_Layout NanoTime Ansys_EMIR_Analysis ESP_CV Liberate_Power_Analysis Verilog BIST DFT Memory_Analysis_Flow_Development +10 more Show less