Principal IC SoC Integration and Design Engineer

Broadcom

Quick summary

Work type
On-site
Location
Mendota Heights, MNFort Collins, COBroomfield, CO
Salary
$129,400–$207,000 / yr
Posted
5 days ago
Closes
Aug 29, 2026

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $195k
This role $168k
$116k most similar roles pay here $255k

This role pays less than 80% of similar roles. Most pay $173,850–$216,250 — the shaded band above. At the midpoint, this role pays about $168k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 98 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 95 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · Principal IC SoC Integration and Design Engineer

Broadcom’s ASIC Product Division seeks a senior-level SoC and IP development engineer to join its high-performance design team. This role involves defining SOC architecture, integrating IP, conducting detailed design analysis with advanced tools, leading simulation and verification efforts, collaborating with internal and external teams for customer success, and optimizing design specifications alongside layout and DFT engineers. The ideal candidate will have extensive experience in SOC architecture using AMBA interconnects, multiple processors, and various IO interfaces, along with expertise in HDL languages like Verilog/VHDL and SystemVerilog, and a strong understanding of physical implementation and timing closure. This position offers the chance to work on cutting-edge AI and storage chip technologies at scale within a leading semiconductor company.

What you'll do

  • Define overall SOC architecture and integrate IP components.
  • Conduct detailed design analysis using advanced tools to ensure quality.
  • Lead team efforts in simulation, synthesis, formal verification, and validation.
  • Optimize SoC area, performance, and yield by consulting with layout engineers.
  • Generate comprehensive design specifications for SoC release documentation.

What we're looking for

  • Experience with SOC architecture using AMBA interconnect and multiple processors
  • Expertise in HDL languages including Verilog, VHDL, and SystemVerilog
  • Strong understanding of physical implementation and timing closure techniques
  • Ability to analyze complex trade-offs and make data-driven decisions
  • Excellent communication and cross-functional collaboration skills
  • Experience with a variety of IO interfaces from basic UART to high-speed DRAM
  • Bachelors in Engineering (EE, CE, or CS) with 12+ years of related experience

More like this

Similar roles

Principal IC Design Engineer

Broadcom

Broomfield, CO +1 37 days ago $127,100$203,400
Verilog VHDL SystemVerilog SOC architecture DRAM interface design Cloud based documentation Signal Integrity Physical implementation Timing closure Process variation HDL languages

SoC Design and Integration Engineer

Qualcomm

San Diego, CA 6 days ago $164,000$246,000
Verilog SystemVerilog VHDL Python Perl Shell TCL Cadence Synopsys Aldec Riviera-PRO ModelSim Xilinx Vivado ASIC design FPGA design RTL Design CI/CD Sub-5nm process nodes Mobile SoC AI SoC Compute SoC XR SoC

Senior SOC Design Engineer

Nvidia

Santa Clara, CA 20 days ago $136,000$218,500
Python Perl RTL EDA SOC integration Design automation Synthesis Padring Physical design
Hybrid

Principal Engineer, SOC Design

Samsung Semiconductor

San Jose, CA +1 24 days ago $219,000$351,000
ASIC RTL Verilog SystemC VHDL Python Perl Tcl CI/CD Git Linux ARM DDR UCIe AMBA DFT STA CDC Lint Synopsys Cadence Mentor Graphics ModelSim QuestaSIM
Hybrid

IC Design Engineer

Broadcom

Fort Collins, CO +1 4 days ago $101,000$162,000
Perl Python Ruby Tcl C++ UNIX/Linux Verilog HDL Object-Oriented Design Git Scan Test Architecture Streaming Scan Networks Bash Digital Timing Analysis

ASIC SoC Design Engineer

Amd

San Jose, CA 25 days ago
Verilog SystemVerilog Python Perl Makefile AMBA AXI APB UPF SDC SVA ASIC CAD tools Simulation Synthesis STA LINT LEC CDC RDC Power estimation
Hybrid