ASIC Physical Design Principal Engineer

Cisco

Remote

Quick summary

Work type
Remote
Location
Remote
Salary
$231,400–$331,800 / yr
Posted
2 days ago
Closes
Aug 1, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $194k
This role $282k
$125k most similar roles pay here $354k

This role pays more than 98% of similar roles. Most pay $169,687–$218,000 — the shaded band above. At the midpoint, this role pays about $282k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 186 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 186 roles with salary data.

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At a glance

TL;DR · ASIC Physical Design Principal Engineer

Role Posting Log in to save

Join the high-impact team at Cisco as a Senior ASIC Design Engineer, where you will focus on RTL-to-GDSII implementation, including logic synthesis and hierarchical floorplanning, while optimizing power, performance, and die size. Your daily tasks will involve analyzing existing tool flows to enhance efficiency, collaborating with various teams to drive best practices, and executing static timing analysis across multi-mode scenarios. You will also guide clock tree synthesis strategies and contribute to automation for STA methodology. Ideal candidates have extensive experience in RTL2GDSII flow and design tapeouts in advanced process technologies like 7nm/5nm/3nm, along with proficiency in EDA tools such as Innovus, Primetime/Tempus, Redhawk/Voltus, and Calibre. Additional skills in hierarchical design, fullchip floor-planning, and scripting languages like Python or TCL are highly valued.

Skills

Innovus Tempus Redhawk Voltus Calibre Python TCL Perl RTL2GDSII Hierarchical_Floorplanning Place_and_Route Static_Timing_Analysis Power_Integrity Equivalence_Checks Clock_Tree_Synthesis STA_setup Timing_Methodologies ECO_Implementation Functional_ECO Timing_ECO Automation Tapeouts 7nm 5nm 3nm

What you'll do

  • Perform RTL-to-GDSII implementation focusing on power, performance, and die-size optimization.
  • Analyze tool flows to identify efficiency gaps and implement enhancements for better design methodology.
  • Guide Clock Tree Synthesis strategies and provide feedback to improve implementation processes.
  • Execute Static Timing Analysis setup and sign-off processes across various scenarios.
  • Implement Functional and Timing ECO using industry-standard flows and contribute to automation.

What we're looking for

  • Extensive experience (7+ years) in ASIC design with advanced degrees.
  • Proficient in RTL-to-GDSII flow and tapeouts for 7nm/5nm/3nm technologies.
  • Expertise in Power Optimization and Analysis methodologies.
  • Skilled in using EDA tools such as Innovus, Primetime/Tempus, Redhawk/Voltus, Calibre.
  • Experience with hierarchical design, timing closure, physical convergence, power integrity.

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