Principal Memory Controller RTL Design Engineer

Microsoft

Quick summary

Work type
On-site
Location
—
Salary
$142,800–$274,800 / yr
Posted
9 days ago
Closes
Dec 15, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $190k
This role $209k
$127k most similar roles pay here $291k

This role pays more than 70% of similar roles. Most pay $168,137–$212,500 — the shaded band above. At the midpoint, this role pays about $209k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 622 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 571 roles with salary data.

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At a glance

TL;DR · Principal Memory Controller RTL Design Engineer

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The Principal Memory Controller RTL Design Engineer will join the Compute Silicon & Manufacturing Engineering team to define and implement micro-architectural specifications in Verilog or System Verilog for high-performance DDR4 or DDR5 memory controllers. This role involves refining designs for optimal area, power, and performance, integrating functional IP into SoC, writing basic tests, and conducting design quality checks such as Lint, CDC/RDC, Low Power Intent, and timing QoR. The engineer will also automate tasks using scripting languages like Perl, Tcl, or Python to enhance efficiency and collaborate with cross-functional teams to deliver high-quality blocks on schedule. Essential skills include proficiency in Verilog/System Verilog, high-speed design principles, front-end tools, synthesis and STA tools, and knowledge of industry-standard interface protocols such as CHI, APB, and AMBA.

Skills

Verilog SystemVerilog Perl Tcl Python Reed-Solomon-Encoding CHI APB AMBA Synthesis STA CDC_checkers low_power_static_checkers linting_tools

What you'll do

  • Define and implement micro-architectural specification in Verilog or System Verilog.
  • Refine implementation for area, power, and performance optimization.
  • Integrate functional IP into SoC for seamless operation.
  • Write basic tests to exercise functionality of the block.
  • Perform design quality checks including Lint, CDC/RDC, Low Power Intent.
  • Automate tasks using scripting languages like Perl, Tcl, Python.

What we're looking for

  • 10+ years designing and implementing high-performance DDR4 or DDR5 memory controllers.
  • Proficient in Verilog/System Verilog coding for area, power, and performance optimization.
  • Strong understanding of digital design principles and SoC/IP development.
  • Expertise in low-power design principles and front-end tools like simulators and checkers.
  • Experience with synthesis and static timing analysis (STA) tools.
  • Scripting skills using Perl, Tcl, Python for automation tasks.
  • Knowledge of industry-standard interface protocols such as CHI, APB, AMBA.

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