Principal Silicon Design Verification Engineer

Microsoft

Quick summary

Work type: On-site
Location: —
Salary: $142,800–$274,800 / yr
Posted: 1 day ago
Closes: Dec 23, 2026

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Competitive pay

How this pay compares to similar roles

Similar $195k

This role $209k

$127k most similar roles pay here $291k

This role pays more than 64% of similar roles. Most pay $173,850–$216,250 — the shaded band above. At the midpoint, this role pays about $209k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 622 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 559 roles with salary data.

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At a glance

TL;DR · Principal Silicon Design Verification Engineer

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As a Principal Engineer in the Data Processing Unit team, you will validate silicon to solve complex datacenter problems by leading key components of functional validation for complex ASIC SOC using UVM/C test benches. You will collaborate with architecture and design teams to develop programmable silicon implementations, defining testing strategies for pre-silicon SoC verification and post-silicon validation. Your responsibilities include developing comprehensive test plans, writing C tests, and creating firmware for chip bring-up while coaching others in your areas of expertise. With a focus on improving validation efficiency through innovative methodologies and tools, you will work with cross-functional teams to influence next-generation designs. This role requires 10+ years of experience in pre-silicon validation, proficiency in Verilog, SystemVerilog, UVM-based testbenches, and knowledge of Ethernet, TCP/IP, ROCEv2, MAC/PCS, and networking NIC/Switches.

Skills

UVM C Verilog SystemVerilog Python Docker CI/CD Kubernetes AWS Azure PostgreSQL Git Jenkins Prometheus Grafana

What you'll do

Lead the functional validation of complex ASIC SOC using UVM/C test bench methodologies.
Define and execute pre-silicon SoC verification and post-silicon validation strategies.
Develop comprehensive test plans, C tests, and infrastructure for complex design validation.
Debug failures, create stress and performance scenarios to meet testing goals effectively.
Innovate and implement methods to enhance validation efficiency and tool usage.

What we're looking for

10+ years of experience in pre-silicon validation for high-performance network devices or CPUs/GPUs.
Extensive knowledge of UVM/C verification methodology and complex SoC development.
Deep understanding of Ethernet, TCP/IP, ROCEv2, MAC/PCS, and networking NIC/Switches.
Strong proficiency in Verilog, System Verilog, and UVM-based testbench environment.
Experience building UVM testbenches and managing regressions to meet coverage goals.

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