Principal Silicon Design Verification Engineer
Microsoft
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How this pay compares to similar roles
This role pays more than 64% of similar roles. Most pay $173,850–$216,250 — the shaded band above. At the midpoint, this role pays about $209k versus about $195k for comparable roles.
Based on 240 similar postings.
Employer
Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing
Microsoft currently has 622 open roles on FindRole.
Listed pay typically runs $119,800–$234,700 across 559 roles with salary data.
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At a glance
Senior Verification Engineer position available for a critical role within the PCIe IP validation team. This individual will be responsible for conducting functional validation of PCIe IP at various levels including block, cluster, and fullchip using UVM/C test benches and verification IPs. Key duties include developing comprehensive test plans, writing unit tests, managing regression suites, debugging failures, and driving timely resolutions to issues. The ideal candidate should possess extensive experience in protocol verification for PCIe Gen6/Gen7 and familiarity with standards like NVMe or RDMA. Strong proficiency in Verilog, SystemVerilog, and UVM-based testbench environments is essential, along with a solid understanding of computer architecture and digital design fundamentals. This role involves innovating to enhance validation efficiency through advanced methodologies and tools, contributing significantly to the successful tapeout of high-scale PCIe IP solutions.
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