Principal Silicon Design Verification Engineer

Microsoft

Quick summary

Work type
On-site
Location
Salary
$142,800–$274,800 / yr
Posted
1 day ago
Closes
Dec 23, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $195k
This role $209k
$127k most similar roles pay here $291k

This role pays more than 64% of similar roles. Most pay $173,850–$216,250 — the shaded band above. At the midpoint, this role pays about $209k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 622 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 559 roles with salary data.

Most-posted roles

View all roles at Microsoft

At a glance

TL;DR · Principal Silicon Design Verification Engineer

Senior Verification Engineer position available for a critical role within the PCIe IP validation team. This individual will be responsible for conducting functional validation of PCIe IP at various levels including block, cluster, and fullchip using UVM/C test benches and verification IPs. Key duties include developing comprehensive test plans, writing unit tests, managing regression suites, debugging failures, and driving timely resolutions to issues. The ideal candidate should possess extensive experience in protocol verification for PCIe Gen6/Gen7 and familiarity with standards like NVMe or RDMA. Strong proficiency in Verilog, SystemVerilog, and UVM-based testbench environments is essential, along with a solid understanding of computer architecture and digital design fundamentals. This role involves innovating to enhance validation efficiency through advanced methodologies and tools, contributing significantly to the successful tapeout of high-scale PCIe IP solutions.

What you'll do

  • Conduct functional validation of PCIe IP at various levels using UVM/C test bench and VIP.
  • Develop comprehensive test plans and unit tests for thorough verification.
  • Manage regression suites, troubleshoot failures, and ensure timely resolution.
  • Enhance validation efficiency by innovating methodologies and tools.
  • Achieve code coverage and functional coverage goals for successful tapeout.

What we're looking for

  • Extensive experience in PCIe protocol verification, including Gen6/Gen7 standards.
  • Proficiency in Verilog, System Verilog, and UVM-based testbench environment.
  • Experience with cluster, SoC, or fullchip level verification for PCIe IP.
  • Strong understanding of computer architecture and digital design fundamentals.
  • Ability to develop and manage regression suites, achieving coverage goals.

More like this

Similar roles

ASIC Design Verification Engineer

Amd

Austin, TX 110 days ago
SystemVerilog UVM C++ Verilog Linux Windows Python Git CI/CD Jenkins Docker Kubernetes AWS Google Cloud Platform PostgreSQL Mentor Graphics Calibre Cadence Incisive Simulator Formal Verification Random Testing Directed Testing

Senior Verification Engineer

Microsoft

32 days ago $119,800$234,700
SystemVerilog UVM C++ PCIe CXL ARM AMBA Python CI/CD Kubernetes Docker AWS Azure Git Jenkins Prometheus Grafana Terraform Ansible PostgreSQL MSSQL