Principal Circuit Design Engineer

Microsoft

Quick summary

Work type
On-site
Location
Salary
$142,800–$274,800 / yr
Posted
5 days ago
Closes
Dec 19, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $185k
This role $209k
$127k most similar roles pay here $291k

This role pays more than 71% of similar roles. Most pay $157,975–$212,718 — the shaded band above. At the midpoint, this role pays about $209k versus about $185k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 622 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 559 roles with salary data.

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At a glance

TL;DR · Principal Circuit Design Engineer

The Principal Circuit Design Engineer role within Microsoft’s Custom IP team focuses on delivering high-quality, cost-effective custom IPs that enhance the Azure Cloud's performance. This senior-level position involves collaborating with SoC designers to develop Memory SRAM and Register file solutions for challenging power-performance-area (PPA) issues. The engineer will work closely with process technology teams to optimize advanced processes and devise methodologies for statistical analysis and characterization of timing, power, and EMIR. Key responsibilities include running quality assurance checks on IP collateral, developing characterization plans for testchips, and creating scripting automation for design flows. Ideal candidates have extensive experience in SRAM/Register file design, process technology understanding, and yield/reliability expertise, along with proficiency in PERL, Python, or TCL scripting and AI integration in circuit design tasks.

What you'll do

  • Develop Memory SRAM and Register file solutions to address complex PPA challenges.
  • Work with process technology teams to understand and leverage advanced DTCO knobs.
  • Create methodologies for statistical analysis and timing/power/EMIR characterization.
  • Conduct quality assurance checks on IP collateral to ensure reliability.
  • Plan and execute post-silicon characterization for inclusion in testchips.
  • Develop scripting automation to enhance design flows efficiency.

What we're looking for

  • 6+ years of SRAM/Register file design experience in advanced process technologies.
  • Expertise in timing, power, EMIR characterization with understanding of DTCO.
  • Proficiency in layout guidance and yield/reliability analysis.
  • Scripting skills in PERL, Python, or TCL for automation.
  • Experience providing technical guidance and multitasking across SoC programs.

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