Principal ASIC Design Engineer

SpaceX

Confirmed live yesterday Low trust

Quick summary

Work type
On-site
Location
Hawthorne, CA
Salary
$200,000–$285,000 / yr
Posted
162 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k
This role $242k
$144k most similar roles pay here $300k

This role pays more than 82% of similar roles. Most pay $177,250–$227,500 — the shaded band above. At the midpoint, this role pays about $242k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 680 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 442 roles with salary data.

Most-posted roles

View all roles at SpaceX

At a glance

TL;DR · Principal ASIC Design Engineer

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As a Principal ASIC Design Engineer on the Starshield team, you will develop next-generation FPGAs and ASICs for space and ground infrastructures supporting national security efforts in earth observation, communications, and hosted payloads. You will be responsible for designing digital ASICs and FPGAs, evaluating architectural trade-offs, defining micro-architecture, and implementing RTL using Verilog or System Verilog. Your daily work involves collaborating with verification teams to ensure design coverage, providing timing constraints for physical implementation, and participating in silicon bring-up and validation. The role requires expertise in multicore CPU subsystem design, standard bus protocols like AXI and AHB, and high-speed, low-power design techniques. You will utilize EDA tools such as VCS, Questa, Spyglass, Vivado, or Quartus II, along with scripting languages like Python and TCL to solve complex hardware problems.

What does a ASIC Design Engineer earn in California?

Median $214000 from 47 postings across 8 companies.

See salary data

Skills

ASIC FPGA Verilog System Verilog RTL Python TCL AXI AHB VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II Synthesis Timing Closure

What you'll do

  • Design digital ASICs and FPGAs for Starshield projects.
  • Evaluate architectural trade-offs based on performance requirements and system limitations.
  • Derive specifications for subsystems and partition functions between hardware and software domains.
  • Implement RTL in Verilog or System Verilog to deliver synthesis and timing clean designs.
  • Provide timing constraints and support the physical implementation team with synthesis and timing closure.
  • Collaborate with verification teams to ensure all design aspects are fully covered.
  • Participate in silicon bring-up, validation, and the development of automated test lab equipment.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • 8+ years of experience in RTL implementation and/or FPGA/ASIC development.
  • Experience with high speed and low power design techniques including clock domain crossings and power optimization.
  • Proficiency in Verilog or System Verilog for micro-architecture and RTL implementation.
  • Experience with standard bus protocols such as AXI and AHB.
  • Proficiency with EDA tools including HDL simulators, lint tools, and FPGA tools.
  • Scripting skills in languages such as Python or TCL.
  • Must be a U.S. citizen, national, permanent resident, or eligible for export control authorizations.

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