Principal ASIC Design Engineer (Starshield)

SpaceX

Quick summary

Work type: On-site
Location: Hawthorne, CA
Salary: $200,000–$285,000 / yr
Posted: today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $177k

This role $242k

$120k most similar roles pay here $303k

This role pays more than 85% of similar roles. Most pay $137,500–$216,900 — the shaded band above. At the midpoint, this role pays about $242k versus about $177k for comparable roles.

Based on 239 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

Most-posted roles

View all roles at SpaceX

At a glance

TL;DR · Principal ASIC Design Engineer (Starshield)

Apply Now Log in to save

As a Principal ASIC Design Engineer at Starshield in Hawthorne, CA, you will join a high-caliber team dedicated to national security projects. Your primary responsibilities include leading the design and implementation of complex RTL and FPGA/ASIC solutions, ensuring adherence to industry standards such as AXI and AHB protocols. You will work on cutting-edge technologies, collaborating closely with hardware architects and software engineers to deliver secure and reliable systems at scale. Ideal candidates possess over 8 years of experience in ASIC development, a deep understanding of digital design methodologies, and proficiency in languages like Verilog or VHDL. This role demands expertise in handling intricate security-related challenges within the aerospace and defense industry.

Skills

AXI AHB RTL FPGA ASIC

What you'll do

Design and implement complex RTL for ASICs using industry-standard protocols.
Optimize FPGA/ASIC designs to meet performance, power, and area requirements.
Develop verification plans and testbenches for comprehensive design validation.
Collaborate on debugging and resolving issues in hardware designs.
Ensure compliance with ITAR regulations throughout the project lifecycle.

What we're looking for

8+ years of experience in RTL implementation and FPGA/ASIC development.
Proficient in AXI, AHB, and other bus protocols.
Strong background in hardware design verification.
Must meet U.S. Department of State ITAR requirements.
Bachelor’s degree or higher in Electrical Engineering or related field.
Extensive experience with ASIC design methodologies and tools.

Save