Principal ASIC Design Engineer (Starshield)

SpaceX

Quick summary

Work type: On-site
Location: Irvine, CA
Salary: $200,000–$285,000 / yr
Posted: today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $177k

This role $242k

$120k most similar roles pay here $303k

This role pays more than 85% of similar roles. Most pay $137,500–$216,900 — the shaded band above. At the midpoint, this role pays about $242k versus about $177k for comparable roles.

Based on 239 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

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At a glance

TL;DR · Principal ASIC Design Engineer (Starshield)

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The Principal ASIC Design Engineer role at Starshield in Irvine, CA is a senior position within the National Security team, requiring 8+ years of experience in RTL implementation and FPGA/ASIC development. This engineer will focus on designing complex digital circuits using AXI, AHB protocols, and other industry standards, contributing to cutting-edge security solutions. The ideal candidate should be proficient in Verilog or SystemVerilog, possess strong knowledge of ASIC design flows, and have experience with EDA tools such as Cadence, Synopsys, or Mentor Graphics. This role involves working on large-scale projects that demand a deep understanding of hardware architecture and the ability to collaborate effectively within a multidisciplinary team addressing critical national security challenges.

Skills

AXI AHB RTL FPGA ASIC

What you'll do

Design and implement complex RTL for FPGA/ASIC development.
Develop and optimize system interfaces using AXI, AHB protocols.
Ensure compliance with ITAR regulations in project execution.
Collaborate on verification of ASIC designs to meet performance specs.
Troubleshoot and resolve issues in RTL implementation and integration.

What we're looking for

8+ years of experience in RTL implementation and FPGA/ASIC development.
Proficiency in AXI, AHB, and other bus protocols.
Strong understanding of ASIC design methodologies.
Experience with ITAR compliance for national security projects.
Bachelor’s degree or higher in Electrical Engineering or related field.

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