Principal ASIC Design Engineer (Starshield)

SpaceX

Quick summary

Work type: On-site
Location: Palo Alto, CA
Salary: $210,000–$295,000 / yr
Posted: today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $177k

This role $252k

$119k most similar roles pay here $314k

This role pays more than 87% of similar roles. Most pay $137,500–$216,900 — the shaded band above. At the midpoint, this role pays about $252k versus about $177k for comparable roles.

Based on 239 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

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At a glance

TL;DR · Principal ASIC Design Engineer (Starshield)

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As a Principal ASIC Design Engineer at Starshield in Palo Alto, CA, you will join the National Security team and lead the design and implementation of complex digital circuits for high-performance computing systems. Your day-to-day responsibilities include developing RTL code, integrating IP blocks, and collaborating with verification engineers to ensure robust functionality. You must have extensive experience with AXI, AHB protocols, and be proficient in Verilog or SystemVerilog. This role demands expertise in FPGA/ASIC development, as well as a deep understanding of digital design principles and methodologies. The position involves working on cutting-edge security technologies at scale, addressing critical business challenges within the national security domain.

Skills

AXI AHB RTL FPGA ASIC

What you'll do

Design and implement complex RTL for ASICs.
Develop and optimize system-level architectures using AXI, AHB protocols.
Collaborate on FPGA prototypes to validate ASIC designs.
Conduct detailed verification of ASIC designs through simulation.
Ensure compliance with ITAR regulations in design processes.

What we're looking for

10+ years of experience in RTL implementation and FPGA/ASIC development.
Proficient in AXI, AHB, and other bus protocols.
Strong understanding of ITAR requirements for U.S. Department of State compliance.
Experience with secure national security projects required.
Bachelor’s degree or equivalent in Electrical Engineering or Computer Science.
Extensive experience in creating high-performance ASIC designs.

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