Browse tech roles

Basic role filtering by workplace, salary floor, and post age. For full AI matching and advanced filtering upload your resume using AI Match.

Active Keyword: Power Management IC Remove filter Clear all

20 of up to 20 (filtered)

CPU Debug and Power Management Verification Engineer

Apple Inc

Beaverton, OR 21 days ago
Actively hiring Confirmed live today High trust
SystemVerilog SVA UVM C++ Python Perl Assembly ARM AXI UPF FPGA Emulation Formal Verification Simulation Power Management Clock Control RTL Scripting
3+ yrs exp
Save

CPU Debug and Power Management Verification Engineer

Apple Inc

Beaverton, OR 21 days ago
Actively hiring Confirmed live yesterday High trust
SystemVerilog SVA UVM C++ Python Perl Assembly ARM AXI UPF FPGA Formal Verification Simulation Emulation Post-Silicon Debug Power Management Clock Control RTL Verification Infrastructure
10+ yrs exp
Save

CPU Processor Power Management Verification Engineer

Apple Inc

Santa Clara, CA 21 days ago $184,700–$324,800
Actively hiring Confirmed live today High trust Above market
System Verilog Verilog UVM Python Perl Assembly Formal Verification UPF FPGA Simulation Emulation Power Management Clock Control RTL Silicon Bringup
10+ yrs exp
Save

CPU Processor Power Management Verification Engineer

Apple Inc

Santa Clara, CA 21 days ago $150,400–$277,600
Actively hiring Confirmed live today High trust Competitive pay
System Verilog Verilog UVM Python Perl Assembly Formal Verification UPF Low Power Simulation FPGA Simulation Emulation RTL Power Management Architecture Clock Control Logic
3+ yrs exp
Save

CPU Processor Power Management Verification Engineer

Apple Inc

Santa Clara, CA 21 days ago $129,300–$194,700
Actively hiring Confirmed live today High trust Below market
System Verilog Verilog Python TCL Perl Assembly Formal Verification RTL FPGA Simulation Emulation Power Management Clock Control Digital Design Computer Architecture
Save

CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Waltham, MA 21 days ago $165,800–$292,400
Actively hiring Confirmed live today High trust Competitive pay
RTL Verilog VHDL Microarchitecture DVFS DVFM C C++ Python Perl Simulation Emulation Formal Methods Power Management Logic Design
10+ yrs exp
Save

CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 21 days ago $184,700–$324,800
Actively hiring Confirmed live today High trust Above market
RTL Verilog VHDL Microarchitecture DVFS DVFM C C++ Python Perl Simulation Emulation Power Management Logic Design
10+ yrs exp
Save

CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Beaverton, OR 21 days ago
Actively hiring Confirmed live today High trust
RTL Verilog VHDL Microarchitecture DVFS DVFM C C++ Python Perl Simulation Emulation Formal Methods Power Management Logic Design Waveform Debugging
10+ yrs exp
Save

CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 21 days ago $150,400–$277,600
Actively hiring Confirmed live today High trust Competitive pay
RTL Verilog VHDL Microarchitecture DVFS DVFM C C++ Python Perl Simulation Emulation Formal Methods Power Management Logic Design
3+ yrs exp
Save

CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 21 days ago $150,400–$277,600
Actively hiring Confirmed live today High trust Competitive pay
RTL Verilog VHDL Microarchitecture DVFS DVFM C C++ Python Perl Simulation Emulation Waveform Debugging Power Management Logic Design
3+ yrs exp
Save

CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Waltham, MA 21 days ago $165,800–$292,400
Actively hiring Confirmed live today High trust Competitive pay
RTL Verilog VHDL Microarchitecture DVFS DVFM C C++ Python Perl Simulation Emulation Formal Methods Waveform Debugging Logic Design Power Management
10+ yrs exp
Save

CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Santa Clara, CA 21 days ago $184,700–$324,800
Actively hiring Confirmed live today High trust Above market
RTL Verilog VHDL Microarchitecture DVFS DVFM C C++ Python Perl Simulation Emulation Power Management Logic Design
10+ yrs exp
Save

CPU Power Management Microarchitect/RTL Engineer

Apple Inc

Beaverton, OR 21 days ago
Actively hiring Confirmed live today High trust
RTL Verilog VHDL Microarchitecture DVFS DVFM C C++ Python Perl Simulation Emulation Formal Methods Power Management Logic Design
10+ yrs exp
Save

CPU Processor Power Management Verification Engineer

Apple Inc

Santa Clara, CA 21 days ago $150,400–$277,600
Actively hiring Confirmed live today High trust Competitive pay
System Verilog UVM Python Perl Assembly Verilog Formal Verification UPF FPGA Simulation Emulation Low Power Simulation Scripting Silicon Debug
3+ yrs exp
Save

CPU Processor Power Management Verification Engineer

Apple Inc

Santa Clara, CA 21 days ago $129,300–$194,700
Actively hiring Confirmed live today High trust Below market
System Verilog Verilog Python TCL Perl Assembly Formal Verification FPGA Simulation Emulation RTL Digital Design Computer Architecture Power Management Clock Control
Save

CPU Processor Power Management Verification Engineer

Apple Inc

Santa Clara, CA 21 days ago $184,700–$324,800
Actively hiring Confirmed live today High trust Above market
System Verilog Verilog UVM Python Perl Assembly Formal Verification UPF FPGA Simulation Emulation Power Management Clock Control RTL
10+ yrs exp
Save

CPU Debug and Power Management Verification Engineer

Apple Inc

Beaverton, OR 21 days ago
Actively hiring Confirmed live today High trust
SystemVerilog SVA UVM C++ Python Perl Assembly ARM AXI UPF FPGA Formal Verification Simulation Emulation Post-Silicon Debug Power Management Clock Control RTL
10+ yrs exp
Save

CPU Debug and Power Management Verification Engineer

Apple Inc

Beaverton, OR 21 days ago
Actively hiring Confirmed live today High trust
SystemVerilog UVM SVA C++ Python Perl Assembly ARM AXI UPF FPGA Formal Verification Simulation Emulation Post-Silicon Debug Power Management Clock Control RTL
3+ yrs exp
Save

Staff Engineer - Power Management IC Design

Qualcomm

Santa Clara, CA 21 days ago $159,600–$239,400
Actively hiring Confirmed live today High trust Competitive pay
Power Management ICs Cadence ADE Spectre MATLAB Verilog Verilog‑AMS SystemVerilog VHDL SPICE Simplis Control Theory Power Electronics Silicon Characterization
6+ yrs exp
Save

Power Management IC Design

Qualcomm

Santa Clara, CA 21 days ago $134,500–$201,700
Actively hiring Confirmed live today High trust Below market
Power Management ICs Cadence ADE Spectre MATLAB Verilog Verilog‑AMS SystemVerilog VHDL SPICE Simplis Control Theory Power Electronics Behavioral Modeling Silicon Characterization
4+ yrs exp
Save