CPU Power Management Microarchitect/RTL Engineer

Apple Inc

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Work type: On-site
Location: Beaverton, OR
Posted: 17 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Similar $221k

$152k most similar roles pay here $291k

This listing doesn't post a salary. Most similar roles pay $187,612–$254,750.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

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TL;DR · CPU Power Management Microarchitect/RTL Engineer

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The CPU Power Management Microarchitect/RTL Engineer joins the Silicon Engineering Group to develop and refine high-performance, low-power microprocessors. This role involves owning micro-architecture development from early exploration through detailed specification, while managing RTL design to meet specific power, performance, area, and timing goals. The engineer will collaborate with multi-functional teams on design delivery, including physical design aspects like reliability and testability, while supporting verification through test bench development and formal methods. Key technical requirements include proficiency in Verilog or VHDL, experience with simulators and waveform debugging, and knowledge of microprocessor architecture. Preferred skills include expertise in dynamic voltage and frequency scaling, thermal management, and power integrity. The role focuses on solving complex problems regarding power state definition, Di/dt mitigation, and advanced low-power microarchitecture techniques for high-performance CPU systems.

Skills

RTL Verilog VHDL Microarchitecture DVFS DVFM C C++ Python Perl Simulation Emulation Formal Methods Power Management Logic Design

What you'll do

Develop and define micro-architecture specifications from high-level exploration to detailed technical requirements.
Own the development, assessment, and refinement of RTL designs to meet power, performance, area, and timing goals.
Support verification teams with test bench development, formal methods, and simulation/emulation for functional verification.
Conduct performance exploration and correlate results to ensure RTL designs meet target performance metrics.
Implement physical design aspects including timing, area, reliability, testability, and power management.
Design and implement advanced power management solutions like DVFS, thermal management, and Di/dt mitigation strategies.
Develop micro-architecture strategies for improved power integrity and asynchronous clock crossing.

What we're looking for

Minimum BS degree and 10+ years of relevant industry experience.
Experience with microprocessor architecture.
Experience with logic design principles involving timing and power implications.
Experience in Verilog or VHDL.
Experience with simulators and the waveform debugging process.
Expertise in advanced power management, thermal management, or clocking solutions (preferred).
Understanding of low power and high-performance microarchitecture techniques (preferred).
Experience in C, C++, Perl, or Python (preferred).