CPU Processor Power Management Verification Engineer

What you'll do

• Verify the functionality correctness of Power Management and Clock Control logic with architecture and RTL designers.
• Develop and execute test plans and schedules for power management and clock control systems.
• Create tests in Assembly, Scripts, SystemVerilog, or vectors for simulation and emulation environments.
• Root cause design failures and propose technical solutions to the design team.
• Develop tests for emulation and FPGA environments to support silicon bringup and debug.
• Create coverage monitors and analyze data to ensure all test cases are fully covered.
• Build checkers and SystemVerilog-based transactors to verify hardware designs.
• Write assertions and apply formal verification techniques to the design.

What we're looking for

• Minimum BS degree and 3+ years of relevant industry experience.
• Experience with digital logic, micro-processor architecture, or power management architecture.
• Experience with digital design verification including Verilog/System-Verilog based testbenches, transactors, and checkers.
• Programming skills in scripting languages such as Perl or Python.
• Master’s degree (preferred).
• Experience in processor or power management architecture and verification (preferred).
• In-depth knowledge of design verification environments like random constraint verification and/or UVM based testbenches (preferred).
• Experience with SystemVerilog assertions, silicon bringup, UPF, low power simulation, formal verification, or assembly language (preferred).