CPU Processor Power Management Verification Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
—
Salary
$129,300–$194,700 / yr
Posted
17 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $201k
This role $162k
$114k most similar roles pay here $268k

This role pays less than 78% of similar roles. Most pay $172,487–$229,100 — the shaded band above. At the midpoint, this role pays about $162k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

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At a glance

TL;DR · CPU Processor Power Management Verification Engineer

The CPU Processor Power Management Verification Engineer joins the processor verification team to focus on power management and clock control logic. This role involves collaborating with architecture and RTL designers to verify functionality correctness, developing test plans, and executing schedules for critical chip design components. The engineer will develop tests in Assembly, Scripts, SystemVerilog, or vectors for simulation and emulation environments while creating coverage monitors and transactors. Additionally, the role involves root cause analysis of failures, writing assertions, and applying formal verification techniques. Key technical requirements include proficiency in Python, Perl, or TCL, along with knowledge of digital logic, microprocessor architecture, and power management systems. The position addresses the complex challenge of ensuring reliable clock control and power management functionality within high-performance processor designs to ensure successful silicon bringup and debug.

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