Power Management IC Design

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$126,700–$190,100 / yr
Posted
38 days ago
Freshness
Confirmed live yesterday
Closes
Jan 31, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $207k
This role $158k
$111k most similar roles pay here $270k

This role pays less than 82% of similar roles. Most pay $171,875–$241,750 — the shaded band above. At the midpoint, this role pays about $158k versus about $207k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Power Management IC Design

The Power Management IC Design role is situated within the PMIC Design team, where the engineer oversees the definition, design, verification, and documentation of mixed-signal integrated circuits. The position focuses on controller ICs and high-current power stage circuitry for compute, data center, automotive, and industrial applications. Responsibilities include determining circuit-level specifications, managing layout execution, performing silicon bring-up, and conducting characterization and debug. The role requires expertise in power electronics, control theory, mixed-signal design, and transistor reliability. Candidates will utilize tools such as Cadence ADE, Spectre, MathWorks MATLAB, Verilog/Verilog-AMS, SystemVerilog, and Simplis to develop complex IC blocks. This position solves critical power management challenges by ensuring designs meet performance specifications across various operating conditions while providing technical guidance on next-generation power management IC development for diverse industrial platforms.

What you'll do

  • Design and verify complex mixed-signal IC blocks and subsystems for power management applications.
  • Develop circuit-level specifications and architectures based on product and platform requirements.
  • Execute architecture implementation and verification using tools like Cadence ADE, Spectre, and MATLAB.
  • Guide layout engineers to produce high-quality layouts and perform physical and reliability verifications.
  • Perform advanced functionality and performance checks across various PVT and operating conditions.
  • Interpret simulation and silicon characterization results to drive corrective design actions.
  • Document detailed design intent, architectural decisions, and circuit functionality for PMIC subsystems.
  • Support silicon bring-up, characterization, and production ramp in collaboration with validation and test teams.

What we're looking for

  • Bachelor's degree in Electrical Engineering with 4+ years of IC Design experience, or a Master's degree with 2+ years of experience, or a PhD.
  • At least 2 years of academic or work experience using Cadence, SPICE, MATLAB, and/or Verilog/VHDL.
  • Expertise in power electronics, control theory, mixed-signal circuit design, or high-speed and high-drive circuits.
  • Experience with advanced topics such as multiphase buck controllers, high-accuracy analog front ends, or transistor reliability.
  • Proficiency in using tools like Cadence ADE, Spectre, MathWorks MATLAB, Verilog/Verilog-AMS, and SystemVerilog.
  • Ability to oversee layout execution, silicon bring-up, characterization, and debug for mixed-signal integrated circuits.
  • Experience in behavioral modeling or mixed-signal verification techniques is preferred.
  • Ability to communicate complex technical information clearly to audiences with varying levels of expertise.

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