CPU Processor Power Management Verification Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
—
Salary
$129,300–$194,700 / yr
Posted
17 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $199k
This role $162k
$115k most similar roles pay here $266k

This role pays less than 78% of similar roles. Most pay $168,762–$229,100 — the shaded band above. At the midpoint, this role pays about $162k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

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At a glance

TL;DR · CPU Processor Power Management Verification Engineer

The CPU Processor Power Management Verification Engineer joins the processor verification team to focus specifically on Power Management and Clock Control verification. In this role, you will collaborate with architecture and RTL designers to verify functionality correctness of power management and clock control logic. Daily responsibilities include developing and executing test plans, creating tests in Assembly, Scripts, SystemVerilog, or vectors for simulation and emulation environments, and root causing failures. You will develop coverage monitors, checkers, and transactors while writing assertions and applying formal verification techniques. The role requires proficiency in Python, Perl, or TCL, along with knowledge of digital logic, microprocessor architecture, and power management architecture. This position addresses the critical technical challenge of ensuring functional correctness within chip design for complex processor systems through rigorous verification methodologies and silicon debug support.

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