CPU Power Management Microarchitect/RTL Engineer

The CPU Power Management Microarchitect/RTL Engineer joins the Silicon Engineering Group to develop high-performance, low-power microprocessors. This role involves owning and participating in micro-architecture development and specification, from early exploration through detailed research. The engineer will manage RTL design refinement to meet specific power, performance, area, and timing goals while supporting verification teams with test bench development, formal methods, and simulation. Key responsibilities include performance exploration, correlation, and physical design implementation for reliability and testability. Candidates must possess expertise in microprocessor architecture, logic design principles, Verilog or VHDL, and waveform debugging. Preferred skills include experience with DVFS/DVFM, thermal management, power state definition, and Di/dt mitigation. The role addresses the technical challenge of creating advanced CPU power management solutions while balancing high-performance requirements with complex power integrity and energy management constraints in microprocessor design.