CPU Power Management Microarchitect/RTL Engineer

The CPU Power Management Microarchitect/RTL Engineer joins the Silicon Engineering Group to develop and refine high-performance, low-power microprocessors. This role involves owning micro-architecture development from early exploration through detailed specification, while managing RTL design to meet specific power, performance, area, and timing goals. The engineer will perform performance exploration, support verification teams with test bench development and formal methods, and collaborate on physical design implementation for reliability and testability. Key technical requirements include expertise in microprocessor architecture, logic design principles, Verilog or VHDL, and experience with simulators and waveform debugging. Preferred skills include knowledge of dynamic voltage and frequency scaling, thermal management, power state definition, and Di/dt mitigation. The role also values proficiency in C, C++, Perl, or Python to address complex power integrity and clocking strategies within the CPU architecture.