CPU Debug and Power Management Verification Engineer

What you'll do

• Verify the functionality of CPU Power Management, clock control, and debug logic.
• Develop and execute comprehensive test plans and schedules across the product lifecycle.
• Write and debug tests in Assembly, SystemVerilog, SVA, C++, and scripting languages.
• Build and maintain verification infrastructure including checkers, transactors, and coverage monitors.
• Analyze functional coverage to ensure complete execution of the test plan.
• Identify, root-cause, and document design issues to drive fixes with RTL teams.
• Support SoC-level debug for clock and power integration issues.
• Perform post-silicon debug using waveform and trace tools across emulation, FPGA, and silicon.

What we're looking for

• Minimum BS degree and 10+ years of relevant industry experience.
• Programming skills in Perl, Python, or SystemVerilog.
• Experience in processor or power management architecture and verification (preferred).
• Experience with system fabric protocols such as AXI (preferred).
• In-depth knowledge in design verification environments like random constraint verification and/or UVM base testbenches (preferred).
• Experience in SystemVerilog assertions, silicon bringup, or UPF and low power simulation (preferred).
• Experience in processor debug features including hardware trace (preferred).
• Experience with advanced verification techniques such as formal verification (preferred).