CPU Processor Power Management Verification Engineer

What you'll do

• Verify the functionality correctness of Power Management and Clock Control logic with architecture and RTL designers.
• Develop and execute test plans and schedules for power management and clock control logic.
• Create tests in Assembly, Scripts, SystemVerilog, or vectors to drive simulation and emulation environments.
• Root cause failures and propose potential solutions to the design team.
• Develop tests for emulation and FPGA environments to support silicon bringup and debug.
• Develop coverage monitors and analyze results to ensure all test cases are covered.
• Create checkers and SystemVerilog-based transactors to verify the design.
• Write assertions and apply formal verification techniques to the design.

What we're looking for

• Minimum BS degree and 10+ years of relevant industry experience.
• Experience in digital logic, micro-processor architecture, or power management architecture.
• Experience with digital design verification including Verilog/System-Verilog based testbenches, transactors, and checkers.
• Experience with design verification environments like random constraint verification or UVM base testbenches.
• Programming skills in Perl or Python.
• Master’s degree (preferred).
• In depth knowledge of power management architecture and design techniques (preferred).
• Experience with SystemVerilog assertions, silicon bringup, UPF, low power simulation, formal verification, or object-oriented programming (preferred).