Staff Engineer - Power Management IC Design

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$153,200–$229,800 / yr
Posted
25 days ago
Freshness
Confirmed live yesterday
Closes
Feb 13, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $194k
This role $192k
$139k most similar roles pay here $240k

This role pays more than 51% of similar roles. Most pay $166,250–$222,250 — the shaded band above. At the midpoint, this role pays about $192k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Staff Engineer - Power Management IC Design

Staff Engineer - Power Management IC Design joins the PMIC Design team to oversee the definition, design, verification, and documentation of mixed-signal integrated circuits. This role focuses on controller ICs and high-current power stage circuitry for compute, data center, automotive, and industrial applications. The engineer will determine circuit-level specifications, manage architecture implementation, perform transistor-level designs, and oversee layout execution and silicon bring-up. Key responsibilities include managing verification strategies, conducting performance checks across PVT conditions, and collaborating with validation teams to ensure production success. Required expertise includes power electronics, control theory, and high-speed circuits. The role utilizes tools such as Cadence ADE, Spectre, MathWorks MATLAB, Verilog/Verilog-AMS, SystemVerilog, and Simplis. Candidates must possess skills in mixed-signal circuit design, behavioral modeling, and transistor reliability to solve complex power management challenges for next-generation products.

What does a Engineer earn in California?

Median $208000 from 94 postings across 22 companies.

See salary data

What you'll do

  • Design and verify complex mixed-signal IC blocks and high-current power stage circuitry for various applications.
  • Execute architecture implementation and circuit design using tools like Cadence ADE, Spectre, and MATLAB.
  • Develop and manage verification strategies for controller circuitry and integrated power management subsystems.
  • Guide layout engineers to produce high-quality layouts and perform physical and reliability verifications.
  • Conduct advanced functionality and performance checks across various PVT and operating conditions.
  • Analyze simulation, characterization, and debug results to drive necessary corrective design actions.
  • Document detailed design intent, architectural decisions, and silicon findings for complex PMIC subsystems.
  • Support silicon bring-up, characterization, and production ramp in collaboration with validation and test teams.

What we're looking for

  • Bachelor's degree in Electrical Engineering with 6+ years of analog, mixed-signal, or Power Management IC design experience.
  • Master's degree in Electrical Engineering or related field with 4+ years of analog, mixed-signal, or Power Management IC design experience.
  • PhD in Electrical Engineering or related field with 2+ years of analog, mixed-signal, or Power Management IC design experience.
  • At least 2 years of academic and/or work experience using CADENCE, SPICE, MATLAB, and/or Verilog/VHDL.
  • Expertise in power electronics, control theory, mixed-signal circuit design, high-speed circuits, or transistor reliability.
  • Proficiency with tools such as Cadence ADE, Spectre, MathWorks MATLAB, Verilog/Verilog-AMS, SystemVerilog, and Simplis.
  • Experience in specific areas like Multiphase Buck Controllers, High-Accuracy Analog Front Ends, or Behavioral Modeling (preferred).

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