Staff Engineer, Power Management IC Design

Qualcomm

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Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$159,600–$239,400 / yr
Posted
40 days ago
Freshness
Confirmed live today
Closes
Mar 16, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $204k
This role $200k
$140k $250k
below market most similar roles pay here above market

This role pays more than 50% of similar roles. Most pay $173,950–$233,400 — the blue band above. At the midpoint, this role pays about $200k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · Staff Engineer, Power Management IC Design

The Staff Engineer - Power Management IC Design joins the PMIC Design team to oversee the definition, design, verification, and documentation of mixed-signal integrated circuits. This role focuses on controller ICs and integrated high-current power stage circuitry for compute, data center, automotive, and industrial applications. The engineer determines IC architecture and circuit-level specifications, managing the full design flow from architecture implementation and simulation through transistor-level circuit design and verification. Key responsibilities include guiding layout execution, performing silicon bring-up, and conducting characterization and debug. Required expertise includes power electronics, control theory, and mixed-signal circuit design. The role utilizes tools such as Cadence ADE, Spectre, MathWorks MATLAB, Verilog/Verilog-AMS, and SystemVerilog to solve complex power management problems and ensure designs meet specifications across various operating conditions.

What does a Engineer earn in California?

Median $199500 from 103 postings across 31 companies.

See salary data

What you'll do

  • Execute architecture implementation, circuit design, and verification of complex IC blocks using Cadence, Spectre, and MATLAB.
  • Own the design and verification strategy for power management IC blocks and high-current power stage interfaces.
  • Guide layout engineers to generate high-quality layouts and conduct physical and reliability verification of circuits.
  • Run advanced functionality and performance checks to ensure designs meet specifications across PVT and operating conditions.
  • Interpret simulation, silicon characterization, and debug results to drive corrective design actions.
  • Document detailed design intent, architectural decisions, circuit functionality, and silicon findings for PMIC subsystems.
  • Support silicon bring-up, characterization, qualification, and production ramp in coordination with validation and test teams.

What we're looking for

  • Bachelor's degree in Electrical Engineering with 6+ years of analog, mixed-signal, or Power Management IC design experience.
  • Master's degree in Electrical Engineering or related field with 4+ years of analog, mixed-signal, or Power Management IC design experience.
  • PhD in Electrical Engineering or related field with 2+ years of analog, mixed-signal, or Power Management IC design experience.
  • 2+ years of academic and/or work experience using CADENCE, SPICE, MATLAB, and/or Verilog/VHDL.
  • Expertise in power electronics, control theory, mixed-signal circuit design, high-speed circuits, or behavioral modeling.
  • Proficiency with design tools including Cadence ADE, Spectre, MathWorks MATLAB, Verilog/Verilog-AMS, and SystemVerilog.
  • Experience in multiphase buck controllers, high-accuracy analog front ends, or transistor reliability (preferred).
  • Experience in mixed-signal verification techniques (preferred).

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