CPU Debug and Power Management Verification Engineer

The CPU Debug and Power Management Verification Engineer joins the silicon engineering team to focus on auxiliary features of a high-performance ARM-based CPU, including power management, clock control, debug infrastructure, resets, and special-purpose registers. This role involves collaborating with architecture and RTL designers across the entire product lifecycle, from pre-silicon test planning to post-silicon bring-up and debug. Responsibilities include developing test plans, building verification infrastructure like checkers and transactors, analyzing functional coverage, and identifying design issues for resolution. The candidate will utilize SystemVerilog, SVA, C++, Assembly, Perl, and Python to validate functionality in simulation, emulation, and FPGA environments. Technical expertise includes UVM base testbenches, AXI protocols, UPF low power simulation, and formal verification. This role addresses the critical challenge of delivering robust, low-power, high-performance CPU designs through rigorous functional verification.