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analog/mixed-signal layout SerDes CMOS Fin-FET LVS DRC ERC ANT ESD Cadence SKILL Python Perl Tcl IC Manufacturing Physical Design Verification Floor-planning Power Distribution Network Clock and Signal Routing +13 more Show less

Mask Layout Design Cadence Virtuoso FinFET CMOS DRC LVS ICV Calibre Python Perl SKILL Mixed-Signal SerDes RF Layout VLSI Floor Planning Tape-out +13 more Show less

PCB Layout Cadence Allegro HDI Signal Integrity DFM DFA DFT Back-drilling EMI/RFI Control IPC Specifications Floor Planning Constraint Management +7 more Show less

PCB Layout Cadence Allegro Mentor Graphics Signal Integrity Power Integrity High-Speed Digital Design EMI/RFI Control ODB++ IPC Specification FCC UL Electronic PCB Documentation CAD Layout Component Placement Constraints Management +10 more Show less

PCB Layout Cadence Allegro Mentor Graphics Signal Integrity Power Integrity High-Speed Digital Design ODB++ EMI/RFI Control IPC Specification FCC UL Electronic PCB Documentation CAD Layout Component Placement Constraints Management +10 more Show less

RFIC Design Custom Layout Cadence Virtuoso XL Siemens Caliber LVS DRC ERC Python SKILL Perl Tapeout Routing Verification AI-assisted tools +9 more Show less

Altium PCB Layout Power Integrity High Speed Digital DDR PCIe SerDes Ethernet USB HDI Microvia Rigid-flex RF Mixed-Signal HyperLynx Ansys SIwave Cadence Sigrity IPC Standards MIL-STD DFM DFA ECAD Libraries +17 more Show less

CMOS Layout Design CADENCE Virtuoso LVS DRC ERC P&R EMIR IR Simulation Floor-planning Standard Cell Planning Hierarchical Layout Assembly Mask Design Physical Design RC Delay Electromigration Cross Capacitance +12 more Show less

SRAM Design Register Files Cadence Virtuoso Calibre LVS/DRC FinFET Nanosheet Static Timing Analysis Monte Carlo Analysis Verilog BIST DFT EMIR Analysis NanoTime Ansys EMIR ESP-CV Liberate SKILL Physical Verification Circuit Simulation Floorplanning +15 more Show less

Silicon Photonics Cadence Virtuoso DRC LVS Python SKILL Perl TCL C++ Calibre Waveguide Routing Tape-out CMOS Pcells ICV Dracula Primeyield Hercules SDL +14 more Show less

CMOS Layout Design CADENCE Virtuoso LVS DRC ERC DFM P&R IR Simulation EMIR floor-planning Standard Cell Planning Hierarchical Layout Electromigration Cross Capacitance Mask Design +11 more Show less

PCB Layout Altium ECAD Signal Integrity Power Integrity High Speed Digital USB PCIe Ethernet DDR DFM DFA MIL-STD IPC BGA Fanout +10 more Show less

PCB Layout Altium ECAD Signal Integrity Power Integrity High Speed Digital USB PCIe Ethernet DDR DFM DFA MIL-STD IPC BGA Fanout Power Distribution Network +11 more Show less

Digital Layout CMOS Floorplanning Standard Cell Planning LVS DRC ERC CADENCE MENTOR GRAPHICS Perl SKILL CSH Physical Design RC Delay Electromigration Memory Compiler Development +11 more Show less

Digital Layout CMOS Floorplanning LVS DRC ERC CADENCE MENTOR GRAPHICS CALIBRE SKILL PERL CSH Memory Compiler Physical Design RC Delay Electromigration +11 more Show less

Digital Layout CMOS LVS DRC ERC Floorplanning Standard Cell Planning Hierarchical Layout Assembly CADENCE MENTOR GRAPHICS CALIBRE Perl SKILL CSH Layout Automation Memory Compiler Development RC Delay Electromigration +13 more Show less

Digital Layout CMOS LVS DRC ERC CALIBRE CADENCE MENTOR GRAPHICS Floorplanning Standard Cell Planning Hierarchical Layout Assembly Perl SKILL CSH Layout Automation Memory Compiler Development RC Delay Electromigration +13 more Show less

RFIC Layout Analog Layout IC Design ASIC Mixed Signal Python Perl Shell Scripting Linux Design Rule Checking Revision Control RFIC Design Tape Out +8 more Show less

RFIC Layout Analog Layout IC Design ASIC Mixed Signal Python Perl Shell Scripting Linux Design Rule Checking Revision Control RFIC Design Silicon Technology +8 more Show less

RFIC Layout Analog Layout ASIC Design Mixed Signal Python Perl Linux Shell Scripting Design Rule Checking Revision Control IC Design Tape Out +7 more Show less