Senior Mask Layout Design Engineer

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Santa Clara, CAAustin, TX
Salary: $132,000–$207,000 / yr
Employment: Full-time
Posted: 21 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $192k

This role $170k

$121k $236k

below market most similar roles pay here above market

This role pays less than 73% of similar roles. Most pay $168,000–$216,250 — the blue band above. At the midpoint, this role pays about $170k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior Mask Layout Design Engineer

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The Senior Mask Layout Design Engineer joins the Dynamic team to handle high-speed mixed-signal circuit designs. In this role, you will perform physical layout for mixed-signal functions including PLLs, high-speed I/O circuits, general I/Os, and ESD structures using innovative sub-micron CMOS technologies. Daily responsibilities involve floor planning, custom layout, and verifying designs against schematics and rules for VLSI products. You will utilize Cadence tools, specifically Virtuoso, and must have tape-out experience with FinFET technology, preferably TSMC N5/N4/N3. Required skills include deep understanding of analog circuit layout, DRC and LVS debugging using ICV or Calibre, and proficiency in scripting languages like Perl, Python, or SKILL. This position solves complex integration problems for high-speed SerDes and RF layout designs within sub-micron CMOS environments.

Skills

Mask Layout Design Cadence Virtuoso FinFET CMOS DRC LVS ICV Calibre Python Perl SKILL Mixed-Signal SerDes RF Layout VLSI Floor Planning Tape-out

What you'll do

Perform physical layout for mixed-signal functions like PLLs, high-speed I/O, and ESD structures.
Execute floor planning and custom layout for innovative sub-micron CMOS technologies.
Verify designs against specific design rules and schematics using Cadence tools.
Customize designs for integration into VLSI products in coordination with ASIC and mixed-signal engineers.
Run and debug DRC and LVS using verification tools such as ICV or Calibre.
Customize DRC and LVS decks to support specific design requirements.
Utilize scripting languages like Perl, Python, or SKILL to automate design tasks.

What we're looking for

Hold a BSEE or equivalent experience.
MSEE is a plus (preferred).
8+ years of relevant mask design / layout experience.
Tape-out experience with FinFET technology is required.
Experience with TSMC N5/N4/N3 is preferred (preferred).
Experience with high-speed SerDes/RF layout design is helpful (preferred).
Experience with top level integration would be excellent to have (preferred).
Validated experience with Cadence custom circuit design tools, particularly Virtuoso.

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