Layout/Mask Designer

As a Layout/Mask Designer, you will join the hardware team to design complex custom layouts for digital circuits using deep SubMicron CMOS technologies. You will collaborate with layout leads and circuit designers to analyze floorplans, plan schedules, and negotiate trade-offs while cleaning up megacells to meet engineering specifications. Your daily responsibilities include interpreting LVS, DRC, ERC, and DFM reports to resolve issues like RC delay, electromigration, self-heating, and cross capacitance. You will utilize advanced CAD tools, including Cadence Virtuoso, and automated P&R tools to achieve best-in-class power, performance, and area results. Additionally, you will perform EMIR simulations to ensure robust power delivery. The role requires expertise in standard cell planning, hierarchical layout assembly, and physical design representation to solve complex technical challenges within the integrated circuit domain.