Digital Layout Design Engineer

Apple Inc

Confirmed live today High trust

Quick summary

Work type
On-site
Location
—
Salary
$166,600–$296,000 / yr
Posted
66 days ago
Freshness
Confirmed live today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $207k
This role $231k
$133k most similar roles pay here $313k

This role pays more than 69% of similar roles. Most pay $170,869–$243,600 — the shaded band above. At the midpoint, this role pays about $231k versus about $207k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

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At a glance

TL;DR · Digital Layout Design Engineer

As a Digital Layout Design Engineer within the Digital Design Engineering group, you will join the microprocessor group to design state-of-the-art ASICs and custom digital macros using advanced technology nodes. You will be responsible for delivering PDV clean layouts for complex digital circuits in deep SubMicron CMOS technologies. Your daily work involves reviewing floorplans with circuit designers, negotiating layout tradeoffs, and interpreting LVS, DRC, and ERC reports to ensure robust physical design representation. You will utilize advanced CAD tools and mask design knowledge to solve technical challenges related to RC delay, electromigration, self-heating, and cross capacitance. The role requires proficiency in floorplanning, standard cell planning, and hierarchical layout assembly. Preferred skills include experience with MENTOR GRAPHICS or CADENCE tools, as well as scripting in CSH, PERL, or SKILL for potential layout automation.

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Digital Layout Design Engineer

Apple Inc

Beaverton, OR 66 days ago
Digital Layout ASIC SubMicron CMOS Floorplanning Standard Cell Planning LVS DRC ERC CALIBRE Mentor Graphics Cadence CSH Perl SKILL Layout Automation Memory Compiler Development
10+ yrs exp