Digital Layout Design Engineer

As a Digital Layout Design Engineer within the microprocessor group, you will join the custom layout team to design state-of-the-art ASICs and digital macros using the latest technology nodes. You will be responsible for delivering PDV clean layouts by designing complex custom layouts for digital circuits in deep SubMicron CMOS technologies. Your daily work involves reviewing floorplans with circuit designers, running verification tools on megacells, and interpreting LVS, DRC, and ERC reports to resolve layout issues efficiently. You will utilize advanced CAD tools and mask design knowledge to ensure robust physical design representation. Required skills include proficiency in floorplanning, standard cell planning, and hierarchical assembly, alongside an understanding of RC delay, electromigration, and self-heating. Experience with MENTOR GRAPHICS or CADENCE tools is required, while scripting in CSH, PERL, or SKILL is a plus.